A semiconductor device includes substrate, a first gate structure, a second gate structure, and an epitaxy layer. The first gate structure and the second gate structure are over the substrate, in which the first gate structure and the second gate structure each comprises a shielding electrode, a gate electrode over the shielding electrode, and a first gate dielectric layer vertically separating the shielding electrode from the gate electrode. The epitaxy layer is over the substrate and cups an underside of the first gate structure and the second gate structure, in which the epitaxy layer comprises a doped region laterally between the first gate dielectric layer of the first gate structure and the first gate dielectric layer of the second gate structure, a dopant concentration of the doped region being non-uniform along a lateral direction.

There is provided a semiconductor device including: a pad portion that is provided above the upper surface of the semiconductor substrate and that is separated from the emitter electrode; a wire wiring portion that is connected to a connection region on an upper surface of the pad portion; a wiring layer that is provided between the semiconductor substrate and the pad portion and that includes a region overlapping the connection region; an interlayer dielectric film that is provided between the wiring layer and the pad portion and that has a through hole below the connection region; a tungsten portion that contains tungsten and that is provided inside the through hole and electrically connects the wiring layer and the pad portion; and a barrier metal layer that contains titanium and that is provided to cover an upper surface of the interlayer dielectric film below the connection region.

A power transistor is formed by a plurality of transistor cells electrically connected in parallel. Each transistor cell includes a gate structure including a gate electrode coupled to a control terminal and a gate dielectric stack, the gate dielectric stack including a ferroelectric insulator. A method of operating the power transistor includes: switching the power transistor in a normal operating mode by applying a switching control signal to the control terminal, the switching control signal having a maximum voltage and a minimum voltage; and setting the ferroelectric insulator into a defined polarization state by applying a first voltage pulse to the control terminal, the first voltage pulse exceeding the maximum voltage of the switching control signal.

A semiconductor device includes a chip having a main surface, an IGBT region formed at the main surface, a diode region formed at the main surface, an insulating film formed on the main surface so as to expose the diode region and so as to cover the IGBT region, a plug electrode embedded in a part, which covers the IGBT region, of the insulating film so as to be partially exposed from the insulating film, and a main surface electrode that includes a first electrode film covering the plug electrode so as to expose the diode region and a second electrode film covering the first electrode film and the diode region.

A semiconductor device includes a chip with a main surface, featuring a first conductivity type base region. A trench gate structure penetrates the base region, while a second conductivity type emitter region is formed along the trench gate structure on the surface. Between the bottom of the base region and the emitter region, a higher impurity concentration in-base region is present. An insulating film covers the main surface, featuring a connection hole that exposes part of the emitter region at a distance from the in-base region. A connection electrode is positioned in the connection hole, electrically connecting the base and emitter regions.

At a front surface of a silicon carbide base, an n.sup.-type drift layer, a p-type base layer, a first n.sup.+-type source region, a second n.sup.+-type source region, and a trench that penetrates the first and the second n.sup.+-type source regions and the p-type base layer and reaches the n-type region are provided. In the trench, the gate electrode is provided via a gate insulating film, an interlayer insulating film is provided in the trench on the gate electrode.

A semiconductor module includes an IGBT device, and a MISFET device that composes a parallel circuit together with the IGBT device. The semiconductor module generates a drain current of the MISFET device in a voltage range less than a built-in voltage of the IGBT device and generates a collector current of the IGBT device and a drain current of the MISFET device in a voltage range equal to or more than the built-in voltage.

A semiconductor device is provided that maintains assembly and improves stress tolerance. The semiconductor device includes a plurality of trenches, a plurality of trench electrodes, an insulation film, and a first electrode. The trench electrodes are provided respectively inside the trenches. The insulation film covers two or more of the trench electrodes. The first electrode is provided on the insulation film. The insulation film has an opening provided between the two or more trench electrodes covered with the insulation film. The first electrode is provided on the semiconductor substrate to fill the opening. Each of the trench electrodes has an upper surface that includes a first recessed portion. The insulation film has an upper surface that includes a second recessed portion located immediately above the first recessed portion. The first electrode has an upper surface that includes a third recessed portion located immediately above the opening.

A method of forming a layered, high power vertical insulated-gate switch uses an n-type substrate. A p-well is formed by implantation in the top surface of the substrate followed by implanting n-type dopants in the p-well to form n+ source regions. Trenched gates are formed extending through the n+ source regions and into the p-well. The wafer is transferred to a carrier and the bottom surface of the wafer substrate is thinned by CMP. An n-buffer layer is then epitaxially grown on the bottom surface using low temperature epitaxy (LTE). The low temperature does not substantially diffuse the dopants in the overlying regions. A bottom p+ layer is then formed by LTE. Anode and cathode metal electrodes are then formed. The n-buffer layer and p+ layers can be precisely formed for optimal efficiency and the LTE maintains the dopant profiles of the overlying regions.

Provided is a semiconductor device, wherein a straight line extending from an end portion E1 in the extending direction of a contact hole for electrically connecting an emitter electrode and a front surface of a semiconductor substrate toward a back surface of the semiconductor substrate is defined as a first perpendicular line, a straight line forming a predetermined angle 1 with respect to the first perpendicular line and passing through the end portion E1 in the extending direction of the contact hole is defined as a first straight line, a position where the first straight line intersects a back surface of the semiconductor substrate is defined as a position M1, and the position M1 is located on an outer side of a cathode region in the extending direction.