INSULATED GATE POWER DEVICE WITH EPITAXIALLY GROWN SUBSTRATE LAYERS

Abstract

A method of forming a layered, high power vertical insulated-gate switch uses an n-type substrate. A p-well is formed by implantation in the top surface of the substrate followed by implanting n-type dopants in the p-well to form n+ source regions. Trenched gates are formed extending through the n+ source regions and into the p-well. The wafer is transferred to a carrier and the bottom surface of the wafer substrate is thinned by CMP. An n-buffer layer is then epitaxially grown on the bottom surface using low temperature epitaxy (LTE). The low temperature does not substantially diffuse the dopants in the overlying regions. A bottom p+ layer is then formed by LTE. Anode and cathode metal electrodes are then formed. The n-buffer layer and p+ layers can be precisely formed for optimal efficiency and the LTE maintains the dopant profiles of the overlying regions.

Claims

1. A method of forming an insulated-gate switching device comprising: providing an n-type substrate having a first n-type dopant concentration, the substrate having a top surface and a bottom surface; doping the top surface with p-type dopants to form a first p-type layer; forming an array of insulated gates; forming n-type source regions overlying at least portions of the first p-type layer; thinning the bottom surface of the substrate; using a low temperature epitaxy (LTE) process to form an n-type buffer layer on the bottom surface of the substrate, where the n-type buffer layer has a dopant concentration that is greater than the first dopant concentration of the n-type substrate; using an LTE process to form a second p-type layer on the n-type buffer layer; forming an anode electrode on the second p-type layer; and forming a cathode electrode electrically connected to the n-type source regions.

2. The method of claim 1 wherein the LTE process forms the n-type buffer layer and the second p-type layer at a temperature of less than 600 C.

3. The method of claim 1 wherein the step of thinning the bottom surface of the substrate thins the substrate to less than 100 microns.

4. The method of claim 1 wherein the step of forming the array of insulated gates comprises: forming trenches at least within the first p-type layer; insulating walls of the trenches; and at least partially filling the trenches with a conductive material.

5. The method of claim 4 wherein the trenches terminate within the first p-type layer.

6. The method of claim 4 wherein the trenches extend below the first p-type layer.

7. The method of claim 1 wherein the first p-type layer forms a well region.

8. The method of claim 1 wherein the method forms an insulated gate turn off device.

9. The method of claim 1 wherein the method forms an insulated gate bipolar transistor.

10. The method of claim 1 wherein the step of forming the array of insulated gates comprises forming an array of vertical gates.

11. The method of claim 1 wherein the step of forming the cathode occurs prior to thinning the bottom surface of the substrate.

12. The method of claim 1 wherein the step of doping the top surface substrate with p-type dopants to form the first p-type layer comprises implanting p-type dopants and then annealing the top surface of the substrate.

13. The method of claim 1 wherein the step of forming n-type source regions overlying at least portions of the first p-type layer comprises implanting n-type dopants in the first p-type layer and then annealing the top surface of the substrate.

14. The method of claim 1 wherein the n-type buffer layer and the second p-type layer are each less than 10 microns thick.

15. An insulated-gate switching device comprising: an n-type substrate having a first n-type dopant concentration, the substrate having a top surface and a bottom surface; a first p-type layer formed within the top surface of the substrate; an array of insulated gates; n-type source regions formed within the first p-type layer; wherein the bottom of the substrate is thinned after forming the first p-type layer, the array of insulate gates, and the n-type source regions; an n-type buffer layer on the bottom surface of the substrate that is formed using a low temperature epitaxy (LTE) process, where the n-type buffer layer has a dopant concentration that is greater than a dopant concentration of the n-type substrate; a second p-type layer on the n-type buffer layer that is formed using an LTE process; an anode electrode on the second p-type layer; and a cathode electrode electrically connected to the n-type source regions.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0024] FIG. 1 is a cross-sectional view of the assignee's prior art vertical insulated-gate switch, formed as a die, from U.S. Pat. No. 10,181,509.

[0025] FIG. 2 is a cross-sectional view of a starting substrate in accordance with one embodiment of the invention.

[0026] FIG. 3 illustrates a p-layer implanted in the top surface of the substrate or epitaxially grown over the substrate, for forming a p-well.

[0027] FIG. 4 illustrates the formation of an n+ source region layer and oxidized trenches filled with a conductive doped polysilicon.

[0028] FIG. 5 illustrates the backside thinning of the substrate using chemical-mechanical-polishing (CMP) after the wafer is installed in a carrier.

[0029] FIG. 6 illustrates the low temperature epitaxy (LTE) growth of an n-buffer layer on the backside surface of the thinned substrate.

[0030] FIG. 7 illustrates the low temperature epitaxy (LTE) growth of a p+ layer on the backside surface of the thinned substrate.

[0031] FIG. 8 illustrates the formation of the cathode and anode electrodes and top dielectric regions to insulate the cathode metal from the gates.

[0032] Elements that are the same or equivalent are labelled with the same numerals.

DETAILED DESCRIPTION

[0033] The invention is directed to an improved process for forming the bottom portion of vertical switches using npnp or pnpn layers. In the example, the new process will be used to form an IGTO device similar to that of FIG. 1, but many other types of devices, such as IGBTs and thyristors may be formed.

[0034] FIG. 2 is a cross-section of a small portion of a starting n-type silicon substrate 40, which will be later singulated to form dies. The wafer may be 200 mm in diameter. A conventional starting thickness of the substrate 40 is about 675 microns, which provides sufficient mechanical strength during manipulation of the substrate 40. The dopant concentration of the substrate 40 is that needed for a thick depletion layer in the vertical switch to withstand a cathode-anode operating voltage on the order of 600 volts.

[0035] FIG. 3 illustrates the implantation of p-type dopants into the top surface of the substrate 40 to form a p-well 42, which may be similar to the p-well 14 in FIG. 1. In one embodiment, the implant will form a p-well 42 about 10 microns thick. Other thicknesses are contemplated and depend on the desired characteristics of the device. The p-well 42 may be patterned using a conventional masking step. The p-well 42 may be considered a p-type layer since it may also be continuous across the die.

[0036] The p-type dopants are then diffused at a high anneal temperature, such as greater than 1000 C., which activates the dopants and repairs the implant damage in the silicon.

[0037] In FIG. 4, the top surface is masked, and n-type dopants are implanted to form the n+ source regions 44. The n-type dopants are then diffused at a high anneal temperature, such as greater than 1000 C., which activates the dopants and repairs the implant damage in the silicon.

[0038] The top surface is masked to define the locations of the trenched gates. The exposed surface is then etched using reactive ion etching (RIE) to form the trenches 45, which may be on the order of 6-8 microns deep. The trenches 45 are oxidized to form gate oxide 46, and the insulated trenches 45 are filled with a conductive doped polysilicon 48 to form an array of gates 50. Each trench area forms a cell in an array of cells, where all the cells are connected in parallel and operate similarly.

[0039] These upper layers may be conventional. Instead of trenched gates, the gates may be lateral and separated from a p-type channel region by thin gate oxide.

[0040] A metal, top cathode electrode (shown later) may be formed now or at a later stage.

[0041] In FIG. 5, the wafer is mounted in a carrier to expose its bottom side. The substrate is then ground down and polished using CMP to approximately 50-60 microns to form a thinned substrate 54. The thickness depends on the desired operating voltage. Generally, the thickness of the n-layer between the p-well 42 and an n-buffer layer should be about 10 microns for every 100 volts. In the example, the thickness of the thinned substrate 54 is 50-60 microns for a 600 volt device.

[0042] In one embodiment, the grinding and polishing form a thinned center area with a much thicker edge area of the circular wafer. This is referred to as a Taiko process. This technique preserves some of the mechanical robustness of the wafer during processing while thinning the areas where devices are formed.

[0043] In FIG. 6, an n-buffer layer 58 is epitaxially grown on the exposed surface using LTE.

[0044] This may be performed at temperatures between 600-250 C., which is low enough to not substantially diffuse dopants in the upper portion of the device. Therefore, the dopant profiles remain relative fixed. The n-buffer layer 58 is doped while growing so that it has a dopant concentration higher than that of the thinned n-type substrate 54. The n-buffer layer 58 is referred to as a field stop layer.

[0045] The n-buffer layer 58 helps to set the breakdown voltage and reduces hole injection into the thinned substrate 54. The thickness of the n-buffer layer 58 may be a few microns, such as less than 10 microns.

[0046] LTE processes for epitaxially growing silicon are well known. Some examples of LTE are described in U.S. Pat. No. 9,231,094 and the article entitled, Silicon Epitaxy on H-Terminated Si (100) Surfaces at 250 C., by Xiao Deng et al., Appl Surf Sci., Aug. 15, 2016, pages 301-307, both incorporated herein by reference.

[0047] In FIG. 7, a p+ layer 60 is grown using LTE on the bottom surface of the thinned substrate 54. As with the n-buffer layer 58, the low temperature does not substantially affect the dopant profiles of the upper layers. The p+ layer 60 may have a p-type dopant concentration greater than 10E19 cm.sup.3. The p+ layer 60 may have a thickness of a few microns, such as less than 10 microns, and serves as an emitter of the vertical pnp transistor. A thin and precisely formed p+ layer 60 is advantageous for reducing on-resistance, for allowing excess carriers to be rapidly removed from the device during turn-off, and for optimizing the performance of the field stop layer (n-buffer layer 58).

[0048] By using LTE, the p+ layer 60 may be formed to be thinner than using implantation. By forming a thin p+ layer 60, carriers in the thick n-layer between the p-well 42 and the n-buffer layer 58 may be removed, when the device is turned off, by direct transport through the p+ layer 60 to the anode electrode. This adds improved efficiency. The absence of crystalline defects due to implantation also improves efficiency.

[0049] In FIG. 8, the bottom metal anode electrode 64 is formed on the p+ layer 60. The top surface is then masked with a dielectric 66, and a top metal cathode electrode 68 is formed to contact the n+ source regions 44.

[0050] The wafer is then diced, and the dies are packaged to form the vertical switches.

[0051] Due to the reduced diffusion of dopants, by using the LTE processes, a higher density of cells may be formed to further improve efficiency.

[0052] The completed die will be a vertical insulated-gate switching device, such as an IGBT or an IGTO device. In the example, the trenched gates terminate within the p-well 42. However, the gates may terminate below the p-well 42 to create an n-type conductive path between the n+ source regions 44 and the n-type thinned substrate 54 when the device is turned on to form a different type of vertical switch.

[0053] Simulations may be used for determining the optimal region depths, dopant concentrations, and dosages.

[0054] Opposite conductivity type devices are formed by making dopant types the opposite of those describe above. Thus, the bottom of the device may be the cathode.

[0055] While particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that changes and modifications may be made without departing from this invention in its broader aspects and, therefore, the appended claims are to encompass within their scope all such changes and modifications as fall within the true spirit and scope of this invention.