In one embodiment, a power MOSFET cell includes an N+ silicon substrate having a drain electrode. An N-type drift layer is grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed along with a trench having sidewalls. A P-well is formed in the N-type layer, and an N+ source region is formed in the P-well. A gate is formed over the P-well's lateral channel and has a vertical extension into the trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction along the sidewalls to reduce on-resistance. A vertical shield field plate is also located next to the sidewalls and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. A buried layer and sinker enable the use of a topside drain electrode.

A power semiconductor device includes a semiconductor substrate having a drift region, a gate electrode trench in the semiconductor substrate and a field electrode needle trench in the semiconductor substrate. The gate electrode trench extends into the drift region and includes a gate electrode. The gate electrode is arranged in the gate electrode trench and electrically insulated from the drift region by a gate dielectric layer arranged between the gate electrode and the drift region. The field electrode needle trench is laterally spaced from the gate electrode trench and extends into the drift region. The field electrode needle trench includes a field electrode arranged in the field electrode needle trench and electrically insulated from the drift region by a cavity formed between the field electrode and the drift region.

An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p.sup.+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p.sup.+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.

A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

Apparatus and associated methods relate to an edge-termination structure surrounding a high-voltage MOSFET for reducing a peak lateral electric field. The edge-termination structure includes a sequence of annular trenches and semiconductor pillars circumscribing the high-voltage MOSFET. Each of the annular trenches is laterally separated from the other annular trenches by one of the semiconductor pillars. Each of the annular trenches has dielectric sidewalls and a dielectric bottom electrically isolating a conductive core within each of the annular trenches from a drain-biased region of the semiconductor pillar outside of and adjacent to the annular trench. The conductive core of the innermost trench is biased, while the conductive cores of one or more outer trenches are floating. In some embodiments, a surface of an inner semiconductor pillar is biased as well. The peak lateral electric field can advantageously be reduced by physical arrangement of trenches and electrical biasing sequence.

Provided is a semiconductor device, including: a semiconductor substrate including a bulk donor; an active portion provided on the semiconductor substrate; and an edge termination structure portion provided between the active portion and an end side of the semiconductor substrate on a upper surface of the semiconductor substrate; wherein the active portion includes hydrogen, and has a first high concentration region with a higher donor concentration than a bulk donor concentration; and the edge termination structure portion, which is provided in a range that is wider than the first high concentration region in a depth direction of the semiconductor substrate, includes hydrogen, and has a second high concentration region with a higher donor concentration than the bulk donor concentration.

According to one embodiment, a method for manufacturing a semiconductor device comprises making a first opening, ion-implanting an impurity of a second conductivity type, and forming a third semiconductor layer of the second conductivity type. The first opening is made in a second semiconductor layer. The second semiconductor layer is provided on a first semiconductor layer. The first opening extends in a second direction. A dimension in a third direction of an upper part of the first opening is longer than a dimension in the third direction of a lower part of the first opening. The third direction is perpendicular to the first direction and the second direction. The impurity of the second conductivity type is ion-implanted into a side surface of the lower part of the first opening. The third semiconductor layer of the second conductivity type is formed in an interior of the first opening.

A semiconductor device according to an embodiment includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, a fourth semiconductor layer of the second conductivity type, a first electrode connected to the second semiconductor layer and the fourth semiconductor layer, a second electrode facing the second semiconductor layer with an insulating film interposed, a fifth semiconductor layer of the second conductivity type, a sixth semiconductor layer of the first conductivity type, a seventh semiconductor layer of the second conductivity type, a third electrode connected to the fifth semiconductor layer and the seventh semiconductor layer, and a fourth electrode facing the fifth semiconductor layer with an insulating film interposed.

A vertical power switching device, such as a vertical superjunction metal-oxide-semiconductor field-effect-transistor (MOSFET), in which termination structures in the corners of the integrated circuit are stretched to efficiently shape the lateral electric field. Termination structures in the device include such features as doped regions, field plates, insulator films, and high-voltage conductive regions and elements at the applied substrate voltage. Edges of these termination structures are shaped and placed according to a 2.sup.nd-order smooth, non-circular analytic function so as to extend deeper into the die corner from the core region of the device than a constant-distance path. Also disclosed are electrically floating guard rings in the termination region, to inhibit triggering of parasitic p-n-p-n structures.

Various improvements in vertical transistors, such as IGBTs, are disclosed. The improvements include forming periodic highly-doped p-type emitter dots in the top surface region of a growth substrate, followed by growing the various transistor layers, followed by grounding down the bottom surface of the substrate, followed by a wet etch of the bottom surface to expose the heavily doped p+ layer. A metal contact is then formed over the p+ layer. In another improvement, edge termination structures utilize p-dopants implanted in trenches to create deep p-regions for shaping the electric field, and shallow p-regions between the trenches for rapidly removing holes after turn-off. In another improvement, a dual buffer layer using an n-layer and distributed n+ regions improves breakdown voltage and saturation voltage. In another improvement, p-zones of different concentrations in a termination structure are formed by varying pitches of trenches. In another improvement, beveled saw streets increase breakdown voltage.