A semiconductor device (1A) includes a chip (2) that includes an SiC monocrystal and has a main surface (3), a trench structure (20) that has a first side wall (22A) extending in an a-axis direction of the SiC monocrystal and a second side wall (22B) extending in an m-axis direction of the SiC monocrystal and is formed in the main surface, and a contact region (50) of a first conductivity type that is formed in a region inside the chip along the trench structure at an interval in the a-axis direction from the second side wall.

We herein describe a semiconductor device comprising a first element portion formed on a substrate, the first element portion being an operating region of an insulated gate bipolar transistor (IGBT) and a second element portion formed on the substrate, the second element portion being an operating region of a diode. The first element portion comprises a first collector region of a second conductivity type, a drift region of a first conductivity type located over the first collector region, and formed by the semiconductor substrate, a first body region of a first conductivity type located over the drift region, a second body region of a second conductivity type located over the drift region, at least one first contact region of a first conductivity type located above the second body region and having a higher doping concentration compared to the first body region, at least one second contact region of a second conductivity type located laterally adjacent to the at least one first contact region, the at least one second contact region having a higher doping concentration than the second body region, a first plurality of trenches extending from a surface through the second body region of a second conductivity type into the drift region wherein the at least one first contact region adjoins at least one of the plurality of trenches so that, in use, a channel region is formed along said at least one trench of the first plurality of trenches and within the body region of a second conductivity type. A first trench of the first plurality of trenches is laterally spaced from a second trench of the first plurality of trenches by a first distance. The second element portion comprises a second collector region of a second conductivity type, the drift region of a first conductivity type located over the second collector region, a third body region of a second conductivity type located over the drift region, a second plurality of trenches extending from a surface through the third body region into the drift region. A first trench of the second plurality of trenches is laterally spaced from a second trench of the second plurality of trenches by a second distance, and the first distance is larger than the second distance. The semiconductor device further comprises a first terminal contact, wherein the first terminal contact is electrically connected to the at least one first contact region of a first conductivity type and the body region of a second conductivity type and a second terminal contact, wherein the second terminal contact is electrically connected to the first collector region and the second collector region.

An SiC semiconductor device includes an SiC semiconductor layer having a first main surface and a second main surface, a gate electrode embedded in a trench with a gate insulating layer, a source region of a first conductivity type formed in a side of the trench in a surface layer portion of the first main surface, a body region of a second conductivity type formed in a region at the second main surface side with respect to the source region in the surface layer portion of the first main surface, a drift region of the first conductivity type formed in a region at the second main surface side in the SiC semiconductor layer, and a contact region of the second conductivity type having an impurity concentration of not more than 1.010.sup.20 cm.sup.3 and formed in the surface layer portion of the first main surface.

An integrated circuit transistor device includes a semiconductor substrate providing a drain, a first doped region in the semiconductor substrate providing a source and a second doped region buried in the semiconductor substrate providing a body. A trench extends into the semiconductor substrate and passes through the first and second doped regions. An insulated polygate region within the trench surrounds a polyoxide region. The polygate region is formed by a first gate lobe and second gate lobe on opposite sides of the polyoxide region and a gate bridge over the polyoxide region. At a first region the gate bridge has a first thickness, and at a second region the gate bridge has a second thickness (greater than the first thickness). At the second region, a gate contact is provided at each trench to extend partially into the second thickness of the gate bridge.

A semiconductor device is provided that maintains assembly and improves stress tolerance. The semiconductor device includes a plurality of trenches, a plurality of trench electrodes, an insulation film, and a first electrode. The trench electrodes are provided respectively inside the trenches. The insulation film covers two or more of the trench electrodes. The first electrode is provided on the insulation film. The insulation film has an opening provided between the two or more trench electrodes covered with the insulation film. The first electrode is provided on the semiconductor substrate to fill the opening. Each of the trench electrodes has an upper surface that includes a first recessed portion. The insulation film has an upper surface that includes a second recessed portion located immediately above the first recessed portion. The first electrode has an upper surface that includes a third recessed portion located immediately above the opening.

There is provided a semiconductor device in which thickness variation of a substrate is precisely controlled. The semiconductor device includes a substrate comprising cell regions, a dummy region between the cell regions, an upper surface and a lower surface opposite the upper surface in a first direction, an active pattern disposed on the upper surface of the substrate, the active pattern comprising a lower pattern extending in a second direction crossing the first direction and a plurality of sheet patterns spaced apart in the first direction from each other, the plurality of sheet patterns being disposed in the cell region, a source/drain pattern disposed between the gate structures adjacent to each other, and a buried insulating pattern penetrating the substrate and the lower pattern in the dummy region.

Disclosed is a silicon carbide power semiconductor device and, more particularly, a silicon carbide power semiconductor device capable of improving on-resistance characteristics by contacting at least one lowermost surface of a base or a source with an underlying JFET region.

A semiconductor device includes: a plurality of transistor cells formed in a semiconductor body. The plurality of transistor cells includes: a plurality of stripe-shape gate trenches formed in a first main surface of the semiconductor body; and a plurality of field plate trenches separate from the stripe-shape gate trenches. At least one field plate trench is laterally interposed between each pair of neighboring stripe-shape gate trenches. Each stripe-shape gate trench includes a gate electrode, a gate dielectric between the gate electrode and a sidewall of the stripe-shape gate trench, and an oxide between the gate electrode and a bottom of the stripe-shape gate trench, the oxide having a vertical thickness that is greater than eight times a lateral thickness of the gate dielectric and/or greater than a vertical thickness of the gate electrode. A method of producing the semiconductor device is also described.

A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.

A semiconductor device is an IGBT of a trench-gate structure and has a storage region directly beneath a p.sup.-type base region. The semiconductor device has gate trenches and dummy trenches as trenches configuring the trench-gate structure. An interval (mesa width) at which the trenches are disposed is in a range of 0.7 m to 2 m. In each of the gate trenches, a gate electrode of a gate potential is provided via a first gate insulating film. In each of the dummy trenches, a dummy gate electrode of an emitter potential is provided via a second gate insulating film. A total number of the gate electrode is in a range of 60% to 84% of a total number of the dummy electrodes.