SILICON CARBIDE POWER SEMICONDUCTOR DEVICE

Abstract

Disclosed is a silicon carbide power semiconductor device and, more particularly, a silicon carbide power semiconductor device capable of improving on-resistance characteristics by contacting at least one lowermost surface of a base or a source with an underlying JFET region.

Claims

1. A silicon carbide power semiconductor device, comprising: a substrate; a drift region having a second conductivity type on the substrate; a JFET region having the second conductivity type on the drift region; a shield region having a first conductivity type on the drift region; a source having the second conductivity type on the shield region; a base having the second conductivity type, on the shield region between the source and the JFET region; a gate including a gate insulating layer on the JFET region and a gate electrode on the gate insulating layer, a source metal on the source; and a drain metal on a lowermost surface of the substrate, wherein the shield region has one or more openings therein.

2. The silicon carbide power semiconductor device of claim 1, wherein the one or more openings are under the source.

3. The silicon carbide power semiconductor device of claim 2, comprising a plurality of the openings, spaced apart from each other.

4. The silicon carbide power semiconductor device of claim 2, wherein the JFET region contacts a lowermost surface of the source and/or base through the one or more openings.

5. The silicon carbide power semiconductor device of claim 2, wherein the JFET region has a lowermost surface at a position deeper than that of the shield region.

6. The silicon carbide power semiconductor device of claim 2, further comprising: a highly doped region having the first conductivity type, adjacent to or in contact with the source.

7. A silicon carbide power semiconductor device, comprising: a substrate; a drift region of having the second conductivity type on the substrate; a JFET region having the second conductivity type, above the drift region; a shield region having a first conductivity type on the drift region; a base having the second conductivity type, on the shield region and having a sidewall in contact with the JFET region; a source having the second conductivity type on the shield region; and a gate including a gate insulating layer on the JFET region and a gate electrode on the gate insulating layer, wherein the base has at least one lowermost surface in contact with the JFET region.

8. The silicon carbide power semiconductor device of claim 7, wherein the shield region has a varying width as the shield region extends along a length direction.

9. The silicon carbide power semiconductor device of claim 7, wherein the shield region is continuous along a width direction.

10. The silicon carbide power semiconductor device of claim 9, wherein the shield region has a sidewall under the gate with a plurality of alternating protrusions and recesses.

11. The silicon carbide power semiconductor device of claim 10, wherein the protrusions are in contact with entire lowermost surfaces of the source and the base along the width direction.

12. The silicon carbide power semiconductor device of claim 10, wherein the lowermost surface of the base contacts the JFET region in the recesses.

13. The silicon carbide power semiconductor device of claim 9, wherein the JFET region comprises: a subregion immediately below the gate; and a carrier storage layer in contact with a lowermost surface of the shield region.

14. The silicon carbide power semiconductor device of claim 9, comprising first and second shield regions on opposite sides of the gate that are symmetrical or asymmetrical to each other with respect to a central axis or plane of the gate along a length direction.

15. A silicon carbide power semiconductor device, comprising: a substrate; a drift region on the substrate; a JFET region on the drift region; a shield region on the drift region; a source on the shield region; a base on the shield region, between the source and the JFET region; and a gate on the JFET region, wherein the base and/or the source has a lowermost surface that contacts the JFET region.

16. The silicon carbide power semiconductor device of claim 15, wherein the shield region comprises an opening, and the JFET region is in contact with the source and/or the base through the opening.

17. The silicon carbide power semiconductor device of claim 16, wherein the source, the base, and the drift region comprise impurity-doped regions having a same conductivity type.

18. The silicon carbide power semiconductor device of claim 16, wherein the shield region comprises a plurality of openings, and the plurality of openings are spaced apart from each other.

19. The silicon carbide power semiconductor device of claim 15, wherein the shield region has a sidewall spaced apart from a sidewall of the base adjacent to the gate.

20. The silicon carbide power semiconductor device of claim 15, wherein the base has a lowermost surface at a position higher than that of the source.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The above and other objectives, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description when taken in conjunction with the accompanying drawings, in which:

[0045] FIGS. 1A and 1B are cross-sectional views of a conventional silicon carbide power semiconductor device;

[0046] FIG. 2 is a plan view of a silicon carbide power semiconductor device according to a first embodiment of the present disclosure;

[0047] FIG. 3 is a cross-sectional view along the line A-A in FIG. 2;

[0048] FIG. 4 is a cross-sectional view along the line B-B in FIG. 2;

[0049] FIGS. 5-6 are cross-sectional views of alternative embodiments of the silicon carbide power semiconductor device shown in FIG. 4;

[0050] FIG. 7 is a plan view of a silicon carbide power semiconductor device according to a second embodiment of the present disclosure;

[0051] FIG. 8 is a cross-sectional view along the line C-C in FIG. 7; and

[0052] FIG. 9 is a cross-sectional view along the line D-D in FIG. 7.

DETAILED DESCRIPTION OF THE INVENTION

[0053] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. The embodiments of the present disclosure may be modified in various forms, and the scope of the present disclosure should not be construed as being limited to the following embodiments, but should be construed based on the matters described in the claims. In addition, the embodiments are provided only for reference, in order to more completely explain the present disclosure to those skilled in the art.

[0054] As used herein, the singular form may include the plural form, unless the context clearly indicates otherwise. In addition, as used herein, the terms comprise and comprising specify the presence of the recited shapes, numbers, steps, operations, members, elements, and/or groups thereof, but do not exclude the presence or addition of one or more other shapes, numbers, steps, operations, members, elements, and/or groups thereof.

[0055] Hereinafter, it should be noted that when one component (or layer) is described as being on another component (or layer), the one component may be directly on the other component, or one or more third components or layers may be between the one component and the other component. In addition, when one component is expressed as being directly on or above another component, no other components are between the one component and the other component. Moreover, being located on top, upper, lower, above, below or one (first) side or an opposite side of a component refers to a relative positional relationship.

[0056] Hereinafter, a first conductivity type impurity region will be understood as, for example, a P-type or N-type doped region, and a second conductivity type impurity region will be understood as a doped region having the other type (i.e., N-type or P-type). In some cases, the first conductivity type impurity region may be a P-type region and the second conductivity type impurity region may be an N-type doped region, but there is no limitation thereto.

[0057] In addition, in the Figures showing a plan view, the x-axis direction is referred to as the width direction and the y-axis direction is referred to as the length direction. It should be noted that for convenience of description and to show a clear structure of a shield region in the plan view, only portions of the gate electrode, the shield region and the JFET region are specifically expressed.

[0058] A silicon carbide power semiconductor device 1 to be described below is preferably an accumulation mode MOSFET (hereinafter referred to as ACCUFET).

[0059] FIG. 2 is a plan view of a silicon carbide power semiconductor device according to a first embodiment of the present disclosure; FIG. 3 is a cross-sectional view along the line A-A in FIG. 2; and FIG. 4 is a cross-sectional view along the line B-B in FIG. 2 and FIGS. 5-6 are alternative embodiments of the silicon carbide power semiconductor device shown in FIG. 4. For convenience of description, it should be noted that components omitted from the plan view of FIG. 2 are shown in the cross-sectional views of FIGS. 3-6.

[0060] Hereinafter, a silicon carbide power semiconductor device 1 according to a first embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0061] Referring to FIGS. 2 to 6, the present disclosure relates to a silicon carbide power semiconductor device 1 and, more particularly, to a silicon carbide power semiconductor device 1 capable of improving on-resistance characteristics of the device by including a shield region (or well region) 140 below a gate 160 with an opening therein.

[0062] First, referring to FIGS. 2 to 4, the silicon carbide power semiconductor device 1 according to a first embodiment of the present disclosure may include a substrate 101. The substrate 101 may include, for example, a silicon carbide (SiC) wafer doped with a high concentration of impurities having a second conductivity type. To be specific, the substrate 101 may be or comprise, for example, a 4H-SiC or 6H-SiC substrate. In addition, the second conductivity-type impurity in the substrate 101 may include, for example, phosphorus.

[0063] A drift region 110 may be on the substrate 101. The drift region 110 may include, for example, a SiC epitaxial layer grown on the upper surface of the SiC single crystal substrate 101, while maintaining a specific crystal orientation relationship with the crystal orientation of the substrate 101, but the scope of the present invention is not limited thereto. In addition, the drift region 110 may comprise a polytype silicon carbide layer, and may comprise a low-concentration impurity doped region having the second conductivity type. The drift region 110 may be formed by, for example, chemical vapor deposition (CVD), but is not limited thereto and may be formed by various processes such as molecular beam epitaxy (MBE), sublimation epitaxy, and liquid phase epitaxy.

[0064] A JFET region 130 may be in or on the drift region 110. The JFET region 130 comprises a highly doped region having the second conductivity type and may be formed by epitaxial growth or an ion implantation process. The JFET region 130 may have a uniform or non-uniform impurity doping concentration. To describe the structure of the JFET region 130 in detail, the JFET region 130 may be between a pair of adjacent bases 151 and shield regions 140 (e.g., along the width direction) and surround the lowermost surface of the shield region 140.

[0065] That is, at least part of the JFET region 130 may be deeper than the lowermost surfaces of the shield region 140 and a heavily doped region 153 to surround the regions 140 and 153 in the drift region 110 or on the drift region 110. By forming the JFET region 130 in this way, when a current flows from a drain metal 180 to a source metal 170, which will be described later, the corresponding current may move through not only a region 131 immediately below the gate 160 but also a lower region 133 contacting the lowermost surface of the shield region 140, current distribution due to the addition of the current movement path may be possible. Accordingly, an effect of improving the on-resistance characteristics of the device may be obtained. That is, the region 133 of the JFET region 130 may comprise a carrier storage layer (hereinafter referred to as CSL) function.

[0066] However, in some cases, the JFET region 130 may include the region 131 immediately below the gate 160, separate from the lower region 133 contacting the lowermost surface of the shield region 140. As such, when the CSL is not formed, in the gate turn-on state, that is, the switch-on state, the current may flow below the shield region 140 and may spread at about 45 degrees, thereby avoiding the shield region 140, and thus the entire current flow may be hindered, causing an increase in on-resistance.

[0067] The shield region 140 may be in or on the drift region 110 or the JFET region 130. The shield region 140 may comprise an impurity-doped region having a first conductivity type. In general, the ACCUFET has a structure in which the source 150 having the second conductivity type, the base 151 having the second conductivity type, and the drift region 110 having the second conductivity type are all conductive, so that during low-current forward operation, current flows through the second conductivity type (e.g., N-Type) conduction regions, instead of a PN diode.

[0068] In addition, although it is common that, during reverse operation, the second conductivity type source 150, base 151, and drift region 110 from the drain metal 180 to the source metal 170 are conductive and are not normally off, current does not flow due to a depletion layer in the junction region between the second conductivity type base 151, the shield region 140 having the first conductivity type, and the JFET region 130 therebetween, a detailed description of which will be described later. In this case, the ability of the device 1 to withstand or tolerate high voltages (e.g., >1000 V) may be achieved by depletion between the shield region 140 and the drift region 110.

[0069] However, as described above, in the switch-on state, since the current may flow below the shield region 140 and spread at about 45 degrees to avoid the shield region 140, the entire current flow is hindered, causing an increase in on-resistance. Thus, in terms of the on-resistance of the device 1, it is preferable that the shield region 140 is minimized.

[0070] The source 150 and the base 151 may be in the shield region 140 or on the shield region 140. The source 150 is a region doped with a high concentration of second conductivity type impurities, and may have a higher impurity concentration than the drift region 110. The base 151 is an impurity-doped region having the second conductivity type, and preferably contains a lower concentration of impurities than the source 150. In addition, one side of the base 151 may be in contact with the source 150. Preferably, the base 151 does not completely cover the JFET region 130 below the gate 160. The base 151 may have a shallower depth than the source 150, but the scope of the present disclosure is not limited thereto.

[0071] Referring to FIGS. 2 and 4 to 6, the aforementioned shield region 140 may have an opening 145 along the width direction below the source 150 and/or the base 151. Referring to FIG. 4, for example, the shield region 140 may include a first part 141 under the source 150 and the heavily doped region 153; and a second part 143 under the base 151. the first region 141 and the second part 143 may be spaced apart from each other along the width direction by the opening 145. The JFET region 130, which is an impurity-doped region having the second conductivity type, may be in the opening 145. That is, the JFET region 130 in the opening 145 may be in direct contact with the source 150 and/or the base 151.

[0072] A plurality of openings 145 may be spaced apart from each other along the length direction and may have an island-type shape or arrangement. The openings 145 may be disconnected along the length direction (see FIG. 2). By contrast, when the opening 145 has a stripe or rectangular shape extending along the length direction, the second part 143 may not be connected to the first part 141, and thus, may be floating in the JFET region 130, which is not preferable. The term island-type should be understood to include not only the openings 145 having the same width and separation distance from each other along the length direction, but also different widths and separation distances from each other. A connection portion 147 connecting the first part 141 and the second part 143 may be formed between the pair of adjacent openings 145 along the length direction. The connection portion 147 is a part of the shield region 140 and may be an impurity-doped region having the first conductivity type (see FIG. 2). The first part 141, the second part 143 and the connection portion 147 may have identical chemical compositions and identical thicknesses.

[0073] As previously described, when the opening(s) 145 have an island-type shape, between adjacent openings 145 along the length direction, the shield region 140 (or connection portion 147) may be continuous along the width direction (see FIG. 3) so that the lowermost surfaces of the source 150 and the base 151 thereon do not contact the JFET region 130 in the location(s) of the connection portion 147.

[0074] Hereinafter, the structure of the shield region 140 including the opening 145 (FIG. 4) will be described in detail.

[0075] Referring to FIG. 4, for example, the first part 141 may contact the entire lowermost surfaces of the source 150 and the heavily doped region 153 to be described later (e.g., along the width direction), while the second part 143 may contact only part of the total area of the lowermost surface of the base 151 (e.g., along the width direction). Thus, the base 151 may contact the JFET region 130 by way of the opening 145.

[0076] Alternatively, referring to FIG. 5, the first part 141 may contact only part of the total area of the lowermost surface of the source 150 (e.g., along the width direction), while the second part 143 may contact the entire lowermost surface of the base 151 (e.g., along the width direction). Due to this, the source 150 may contact the JFET region 130 by way of the opening 145.

[0077] In a further alternative, referring to FIG. 6, the first part 141 and the second part 143 may both contact only parts of the total areas of the lowermost surfaces of the source 150 and the base 151 (e.g., in the width direction), respectively, so that part of the source 150 and part of the base 151 may both contact the JFET region 130 through the opening 145.

[0078] Referring back to FIG. 3, as previously mentioned, when the opening 145 has an island type shape or arrangement, for example, the shield region 140 may contact the entire lowermost surfaces of the source 150 and the base 151 between adjacent openings 145 (e.g., along the length direction), or be continuous along the width direction.

[0079] As such, the shield region 140 may be discontinuous along a direction from the source 150 to the base 151, so that the cross-sectional area or volume of the JFET region 130 may be relatively large (e.g., in comparison with an otherwise identical device in which the shield region 140 does not contain any openings), and thus the on-resistance characteristics of the JFET region 130 may improve.

[0080] In addition, during the reverse operation of the device 1, the opening 145 may result in a PNP structure (e.g., a sandwich structure) comprising the first part 141 of the shield region 140 (having the first conductivity type), the JFET region 130 (having the second conductivity type) in the opening 145, and the second part 143 of the shield region 140 (having the first conductivity type) along the width direction. Due to built-in field resulting from such a sandwich structure, the JFET region 130 in the opening 145 is completely depleted, so that the normally-off characteristics of the device 1 may achieved. In this case, the device 1 may be able to withstand or tolerate high voltages as a result of the depletion between the shield region 140 and the drift region 110 therebelow.

[0081] Referring again to FIGS. 2 to 4, the heavily doped region 153 may be adjacent to or in contact with the source 150 and on a side of the source 150 opposite from the base 151. The heavily doped region 153 may be on or in the drift region 110 or the JFET region 130, and may comprise, for example, a region heavily doped with impurities having the first conductivity type.

[0082] In addition, the gate 160 may be on the drift region 110 or the JFET region 130. The gate 160 may at least partially overlap the shield region 140 and the source 150.

[0083] The gate 160 may include a gate oxide layer 161 on the JFET region 140 and a gate electrode 163 on the gate oxide layer 161. The gate oxide layer 161 may also be on the base 151 and at least part of the source 150. The gate electrode 163 may comprise, for example, a polysilicon layer doped with impurities. In addition, an insulating layer 165 may surround the gate electrode 163 and the gate oxide layer 161. The insulating layer 165 covers sidewalls of the gate electrode 163 and may at least partially cover an upper surface of the gate electrode 163 (e.g., the insulating layer 165 may have an opening therein for a conductive contact or via to contact the gate electrode 163). The gate 160 may have a stripe (e.g., rectangular) and/or planar shape, but the scope of the present disclosure is not limited thereto.

[0084] The source metal 170 may be on or over the substrate 101, the JFET region 130, the source 150, and/or the heavily doped region 153. The source metal 170 may cover the insulating layer 165, and may include nickel (Ni) or aluminum (Al), but is not limited thereto. The source metal 170 may make ohmic contact with the source 150 and the heavily doped region 153.

[0085] The drain metal 180 may be on the lowermost surface of the substrate 101. The drain metal 180 may be electrically connected to a drain terminal (not shown). For example, the drain metal 180 may include nickel (Ni) or silver (Ag), but is not limited thereto.

[0086] FIG. 7 is a plan view of a silicon carbide power semiconductor device according to a second embodiment of the present disclosure; FIG. 8 is a cross-sectional view of the silicon carbide power semiconductor device of FIG. 7 along the line CC in FIG. 7; and FIG. 9 is a cross-sectional view of the silicon carbide power semiconductor device of FIG. 7 along the line D-D in FIG. 7.

[0087] Hereinafter, a silicon carbide power semiconductor device 2 according to a second embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. For the structures in the silicon carbide power semiconductor device 2 according to the second embodiment that are substantially the same as in the device 1 according to the first embodiment, a 2 is written at the beginning of the identification number in the drawings, instead of the number 1, and additional explanations related to this will be omitted. In the silicon carbide power semiconductor device 2 according to the second embodiment, only the shield region 240, which is different from that of the first embodiment, will be described in detail.

[0088] Referring to FIGS. 7 to 9, the present disclosure relates to a silicon carbide power semiconductor device 2 and, more particularly, to the silicon carbide power semiconductor device 2 including a continuous shield region 240 (e.g., that is continuous along the width direction), but which exposes parts of the lowermost surface of the base 251, thereby improving the on-resistance characteristics of the device 2.

[0089] Referring to FIG. 7, the shield region 240 according to the second embodiment may have at least one sidewall with a concave-convex or sawtooth shape, or that contains a series of alternating square or rectangular projections and recesses, along the length direction. it may be preferable that the entire sidewall of the shield region 240 has the concavo-convex shape or the series of alternating square or rectangular projections and recesses. That is, the shield region 240 may have a plurality of protrusions 240a and a plurality of recesses 240b along the length direction, and for example, the protrusions 240a and the recesses 240b may alternate and repeat. At this time, the term protrusion refers to a structure protruding or extending toward a central axis or plane of the gate 260 along the length direction in a plan view (e.g., FIG. 7), and recess refers to a structure that complements the protrusion along the length and/or width direction in the plan view. At this time, the shield regions 240 on opposite sides of the gate 160 in FIG. 7 may be symmetrical or asymmetrical along the central axis or plane of the gate 160 in the length direction. In the asymmetrical case, the shield regions 240 may be offset so that the protrusions 240a on one side face the recesses 240b on the other side along the length direction. In addition, although in FIG. 7, the sidewalls having the protrusions 240a and the recesses 240b are shown, some or all of the sidewalls may have a curved shape, and the scope of the present disclosure is not limited by a specific shape.

[0090] Referring to FIGS. 7 and 8, the protrusion 240a may contact the entire lowermost surfaces of the source 250 and the base 251 along the width direction. That is, the protrusion 240a may extend to a boundary or interface between the base 251 and the JFET region 230 or to a point adjacent to the boundary or interface. Accordingly, the protrusion 240a may contact the entire lower potion of the base 251 along the width direction, but may contact only a part of the lowermost surface of the base 251 in some cases. That is, it is sufficient that the sidewall of the protrusion 240a is closer to the center of the gate 260 than the sidewall of the recess 240b.

[0091] Referring to FIGS. 7 and 9, the shield region 240 adjacent to the recess 240b along the width direction generally contacts the entire lowermost surface of the source 250, but the recess 240b exposes at least part of the lowermost surface of the base 251 to the JFET region 130. Since the shield region 240 according to the second embodiment is continuous along the width direction, the lowermost surface of the base 251 adjacent to the JFET region 230 along the width direction may be exposed to the JFET region 230 thereunder.

[0092] In this way, as the shield region 240 has recesses 240b therein, the cross-sectional area or volume of the JFET region 230 may be relatively large, and thus, the on-resistance of the JFET region 230 may improve.

[0093] Furthermore, during the reverse operation of the device 2, a PNP structure comprising the shield region 240 (specifically, the protrusion 240a having the first conductivity type), the JFET region 130 (having the second conductivity type), and another part of the shield region 240 (specifically, another protrusion 240a having the first conductivity type) may be along the length direction. Due to a built-in field resulting from such a PNP structure, the JFET region 130 between the adjacent protrusions 240a in the length direction is completely depleted, to achieve the normally-off characteristics of the device 2. In this case, the device 2 may be able to withstand or tolerate high voltages as a result of the depletion between the shield region 240 and the drift region 210 therebelow.

[0094] The above detailed description is illustrative of the present disclosure. In addition, the above description shows and describes various embodiments of the present disclosure, and the present disclosure can be used in various other combinations, modifications, and environments. In other words, changes or modifications are possible within the scope of the concept of the disclosure herein, the scope equivalent to the disclosure, and/or within the scope of skill or knowledge in the art. The above-described embodiments describes various states for implementing the technical idea of the present disclosure, and various changes for specific applications or fields of use of the present disclosure are possible. Accordingly, the detailed description of the present disclosure is not intended to limit the present disclosure to the disclosed embodiments.