An embodiment semiconductor device includes an N type layer having a trench therein, a P type region within the N type layer, an N+ type region within the P type region, a gate electrode within the trench including a first gate electrode having an upper surface lower than an upper surface of the P type region and a second gate electrode having an upper surface lower than the upper surface of the first gate electrode, and source and drain electrodes insulated from the gate electrode, wherein the N+ type region includes a first N+ type region on a side of the first gate electrode and having a lower surface lower than the upper surface of the first gate electrode and a second N+ type region on a side of the second gate electrode and having a lower surface lower than the lower surface of the first N+ type region.

The trench structure part includes a field plate electrode, a first insulating film, a second insulating film, the second insulating film extending to be more proximate to the first surface than the first insulating film, a gate electrode including a first portion located on the second insulating film, and a second portion located on the first insulating film, the second portion being thicker than the first portion, and a third insulating film. The gate contact part extends from the gate wiring layer toward the second portion and contacts the second portion. The gate contact part is not positioned between the first portion and the gate wiring layer. The first portion is positioned adjacent, in a second direction orthogonal to the first direction, to a lower end portion of the gate contact part contacting the second portion.

The gate electrode includes a first side surface portion facing a region of a side surface of a mesa part, a second side surface portion positioned at a side opposite to the first side surface portion, a bottom portion oblique to the first and second side surface portions, the bottom portion connecting the first side surface portion and the second side surface portion, a first corner portion positioned between the first side surface portion and the bottom portion, and a second corner portion positioned between the second side surface portion and the bottom portion. An angle between a first straight line and a second straight line is not more than 60. The first straight line is a straight line extending in a first direction and passing through the first corner portion. The second straight line is a straight line passing through the first and second corner portions.

The disclosure relates to a semiconductor die with a semiconductor device in a semiconductor body, the semiconductor body comprising a silicon carbide substrate; an epitaxial silicon carbide layer system on a first side of the silicon carbide substrate; an interruption layer; wherein the interruption layer is embedded either into the silicon carbide substrate or into the epitaxial silicon carbide layer system, in each case at a vertical distance from the first side of the silicon carbide substrate.

A semiconductor device includes a chip having a main surface, a trench resistance structure formed in the main surface, a gate pad that has a resistance value lower than that of the trench resistance structure and that is arranged on the trench resistance structure so as to be electrically connected to the trench resistance structure, and a gate wiring line that has a resistance value lower than that of the trench resistance structure and that is arranged on the trench resistance structure so as to be electrically connected to the gate pad via the trench resistance structure.

A method of manufacturing a vertical silicon carbide semiconductor device having an electrode on each of two main surfaces of a semiconductor chip in which an n-type low concentration buffer layer and an epitaxial layer are grown by epitaxy on a silicon carbide substrate. Defects extending from the silicon carbide substrate to the epitaxial layer and defects generated in the epitaxial layer during epitaxial growth are detected by a PL image of the n-type low concentration buffer layer; the defects generated in the epitaxial layer during the epitaxy are detected by a PL image of the epitaxial layer; the defects extending from the silicon carbide substrate to the epitaxial layer are detected by the difference between detection results; and semiconductor chips free of the defects extending from the silicon carbide substrate to the epitaxial layer are identified.

An SiC semiconductor device includes a chip that includes an SiC monocrystal and has a main surface, a trench structure that has a side wall and a bottom wall and is formed in the main surface, and a contact region of a first conductivity type that includes a first region formed in a region along the side wall in a surface layer portion of the main surface and a second region formed in a region along the bottom wall inside the chip and having an impurity concentration lower than an impurity concentration of the first region.

An SiC semiconductor device comprises: a chip that includes an SiC monocrystal and has a main surface; a trench structure that has a first side wall extending in an a-axis direction of the SiC monocrystal and a second side wall extending in an m-axis direction of the SiC monocrystal and is formed in the main surface; and a contact region of a first conductivity type that is formed in a region inside the chip along the trench structure at an interval in the m-axis direction from the first side wall.

A semiconductor device (1A) includes a chip (2) that includes an SiC monocrystal and has a main surface (3), a trench structure (20) that has a first side wall (22A) extending in an a-axis direction of the SiC monocrystal and a second side wall (22B) extending in an m-axis direction of the SiC monocrystal and is formed in the main surface, and a contact region (50) of a first conductivity type that is formed in a region inside the chip along the trench structure at an interval in the a-axis direction from the second side wall.

The present disclosure provides a trench field effect transistor structure and a manufacturing method thereof. The manufacturing method includes: providing a substrate (100), forming an epitaxial layer (101), forming a device trench (102) in the epitaxial layer, and forming a shielding dielectric layer (107), a shielding gate layer (105), a first isolation dielectric layer (108), a gate dielectric layer (109), a gate layer (110), a second isolation dielectric layer (112), a body region (114), a source (115), a source contact hole (118), a source electrode structure (122), and a drain electrode structure (123). During manufacturing of a trench field effect transistor structure, a self-alignment process is adopted in a manufacturing process, so that a cell pitch is not limited by an exposure capability and alignment accuracy of a lithography machine, to further reduce the cell pitch of the device, improve a cell density, and reduce a device channel resistance.