A semiconductor device has a substrate and semiconductor layer formed over the substrate. The semiconductor layer has a first conductivity type. A trench is formed through the semiconductor layer. A semiconductor material having a second conductivity type is deposited over a side surface of the trench by vapor phase deposition or plasma doping. The semiconductor material is diffused into the semiconductor layer to form a first column of semiconductor material having the second conductivity type within the semiconductor layer. A first insulating layer is formed over the side surface of the trench. A body region is formed within the semiconductor layer. A source region is formed within the body region. A gate region is formed within the body region. A second insulating layer is formed over the trench. A third insulating layer is formed over the second insulating layer. A conductive layer is formed over the third insulating layer.

A semiconductor device has a substrate and semiconductor layer formed over the substrate. The semiconductor layer has a first conductivity type. A trench is formed through the semiconductor layer. An epitaxial layer having a second conductivity type is formed over a surface of the semiconductor layer and a side surface of the trench. The epitaxial layer is diffused into the semiconductor layer to form a first column of semiconductor material having the second conductivity type within the semiconductor layer. A first insulating layer is formed over the side surface of the trench. A body region is formed within the semiconductor layer. A source region is formed within the body region. A gate region is formed within the body region. A second insulating layer is formed over the trench. A third insulating layer is formed over the second insulating layer. A conductive layer is formed over the third insulating layer.

A method of manufacturing a semiconductor device is provided, including: forming a first conductive type lightly doped region in the epitaxial layer; forming a first conductive type heavily doped region and a second conductive type heavily doped region in the epitaxial layer on the first conductive type lightly doped region, in which the neighboring first conductive type heavily doped regions are spaced apart by the second conductive type heavily doped region; disposing the mask on the second conductive type heavily doped region; disposing a spacer on a sidewall of the mask; doping a first conductive type dopant in the first conductive type lightly doped region to form an anti-breakdown region; removing the mask and forming a trench extending into the second conductive type heavily doped region, first conductive type lightly doped region and the epitaxial layer; and removing the spacer.

A semiconductor device includes: a plurality of transistor cells formed in a semiconductor body. The plurality of transistor cells includes: a plurality of stripe-shape gate trenches formed in a first main surface of the semiconductor body; and a plurality of field plate trenches separate from the stripe-shape gate trenches. At least one field plate trench is laterally interposed between each pair of neighboring stripe-shape gate trenches. Each stripe-shape gate trench includes a gate electrode, a gate dielectric between the gate electrode and a sidewall of the stripe-shape gate trench, and an oxide between the gate electrode and a bottom of the stripe-shape gate trench, the oxide having a vertical thickness that is greater than eight times a lateral thickness of the gate dielectric and/or greater than a vertical thickness of the gate electrode. A method of producing the semiconductor device is also described.

The present disclosure provides a split gate MOSFET and a manufacturing method thereof. An epitaxy layer with a first conductivity type is formed on a substrate. A plurality of trenches are formed in the epitaxy layer. Impurities with a second conductive type is implanted and driven to the trenches to form a plurality of first doping areas. Since the first doping areas and none-doping areas of the epitaxy layer are alternately arranged with each other, and the first conductive type and the second conductive type are different conductivity types selected from P type or N type, the split gate MOSFET including the super junction structure is manufactured, and the advantages of simplifying manufacturing process, reducing cost and greatly reducing the on-resistance are achieved.

A semiconductor device including an active portion is provided, the semiconductor device comprising: a drift region of a first conductivity type provided in the semiconductor substrate; a base region of a second conductivity type provided above the drift region; a gate pad provided above the semiconductor substrate; an emitter electrode provided above the semiconductor substrate; a gate trench portion provided on a front surface of the semiconductor substrate in the active portion; and a gate wiring portion for connecting the gate pad and the gate trench portion; wherein the gate wiring portion has: a first gate trench wiring portion which extends in a predetermined direction; and a second gate trench wiring portion which extends in a different direction from the first gate trench wiring portion and intersects the first gate trench wiring portion at an intersection portion; and the emitter electrode is provided above the intersection portion.

A semiconductor device includes a semiconductor substrate having an element region and a terminal region located around the element region. The terminal region includes multiple guard rings and multiple first diffusion regions. When the semiconductor substrate is viewed in a plan view, one of the first diffusion regions is arranged correspondingly to one of the guard rings, and each of the guard rings is located in corresponding one of the first diffusion regions. A width of each of the first diffusion regions is larger than a width of corresponding one of the guard rings.

A power semiconductor device includes a semiconductor substrate, a drift layer, a well region, a doped region, two dummy trenches, a gate structure and a dielectric layer. The semiconductor substrate is doped to have a first conductive channel. The drift layer on the semiconductor substrate is doped to have the first conductive channel. The well region on the drift layer is doped to have a second conductive channel having a polarity opposite to that of the first conductive channel. The doped region on the well region is doped to have the first conductive channel. Two dummy trenches pass through the doped region and the well region. Each of the dummy trenches has a dummy gate. The gate structure has a real gate and is between the dummy trenches. The dielectric layer isolates the dummy gate and the real gate from the doped region, the well region and the drift layer.

A semiconductor device includes a gate electrode embedded in each of a plurality of first trenches through an insulating film. The gate electrode includes a first gate electrode electrically connected to a first gate pad and a second gate electrode electrically connected to a second gate pad. A charge period and a discharge period of gate capacitance parasitic on the second gate electrode are shorter than a charge period and a discharge period of gate capacitance parasitic on the first gate electrode, respectively.

A semiconductor device includes an SiC semiconductor layer which has a first main surface on one side and a second main surface on the other side, a semiconductor element which is formed in the first main surface, a raised portion group which includes a plurality of raised portions formed at intervals from each other at the second main surface and has a first portion in which some of the raised portions among the plurality of raised portions overlap each other in a first direction view as viewed in a first direction which is one of the plane directions of the second main surface, and an electrode which is formed on the second main surface and connected to the raised portion group.