A semiconductor device includes an isolation structure in a substrate. The semiconductor device further includes a gate structure over a first region of the substrate, wherein the isolation structure surrounds the first region, the gate structure comprising a first section and a second section. The semiconductor device further includes a conductive field plate over the substrate, the conductive field plate extending between the first section and the second section and overlapping an edge of the first region, wherein the conductive field plate comprises a dielectric layer having a variable thickness. The semiconductor device further includes a first well in the substrate, wherein the first well overlaps the edge of the first region, and the first well extends underneath the isolation structure, and the conductive field plate extends beyond an outer-most edge of the first well.

A Schottky barrier diode includes a semiconductor layer having a plurality of trenches formed by digging in from a top surface and having mesa portions formed between adjacent trenches, and a Schottky metal formed to contact the top surface of the semiconductor layer including inner surfaces of the trenches.

A termination region of an IGBT is described, in which surface p-rings are combined with oxide/polysilicon-filled trenches, buried p-rings and surface field plates, so as to obtain an improved distribution of potential field lines in the termination region. The combination of surface ring termination and deep ring termination offers a significant reduction in the amount silicon area which is required for the termination region.

A chip part according to the present invention includes a substrate having a penetrating hole, a pair of electrodes formed on a front surface of the substrate and including one electrode overlapping the penetrating hole in a plan view and another electrode facing the one electrode, and an element formed on the front surface side of the substrate and electrically connected to the pair of electrodes.

An object of the present invention is to provide a semiconductor device capable of eliminating unevenness of current distribution in a plane. A semiconductor device according to the present invention is a semiconductor device including a transistor cell region where a plurality of transistor cells is arranged on a semiconductor substrate, the semiconductor device including an electrode pad which is arranged avoiding the transistor cell region on the semiconductor substrate and is electrically connected to a one-side current electrode of each of the cells, in which the transistor cell region contains a plurality of regions each of which has a different current drive capability from each other depending on a distance from the electrode pad.

An ESD protection semiconductor device includes a substrate, a buried layer buried in the substrate, a first well formed in the substrate, a first doped region formed in the first well, a second doped region formed in the first well and adjacent to the first doped region, a second well formed in the first well, and a third doped region formed in the second well. The buried layer, the first well, the first doped region, and the third doped region include a first conductivity type while the second doped region and the second well include a second conductivity type complementary to the first conductivity type. The second well is spaced apart from the first doped region and the second doped region by the first well.

A power semiconductor transistor includes a semiconductor body coupled to a load terminal, a drift region, a first trench extending into the semiconductor body and including a control electrode electrically insulated from the semiconductor body by an insulator, a source region arranged laterally adjacent to a sidewall of the first trench and electrically connected to the load terminal, a channel region arranged laterally adjacent to the same trench sidewall as the source region, a second trench extending into the semiconductor body, and a guidance zone electrically connected to the load terminal and extending deeper into the semiconductor body than the first trench. The guidance zone is adjacent the opposite sidewall of the first trench as the source region and adjacent one sidewall of the second trench. In a section arranged deeper than the bottom of the first trench, the guidance zone extends laterally towards the channel region.

Under one aspect, a power Schottky diode includes a cathode; a semiconductor disposed over the cathode, the semiconductor including at least a first region and a second region, the second region defining a guard ring; an anode disposed over the first region and at least a portion of the guard ring, the anode including a metal, a junction between the anode and the first region defining a Schottky barrier; and an oxide disposed over the guard ring. Additionally, the power Schottky diode can include a resistive material disposed over at least a portion of the guard ring and at least a portion of the oxide. The resistive material can inhibit a flow of holes from the guard ring to the anode following a heavy ion strike to the guard ring. The anode further can be disposed over at least a portion of, or the entirety of, the resistive material.

A diode device and manufacturing method thereof are provided. The diode device includes a substrate, an epitaxial layer, a trench gate structure, a Schottky diode structure and a termination structure. An active region and a termination region are defined in the epitaxial layer. The Schottky diode structure and the trench gate structure are located in the active region and the termination structure is located in the termination region. The termination structure includes a termination trench formed in the epitaxial layer, a termination insulating layer, a first spacer, a second spacer and a first doped region. The termination insulating layer is conformingly formed on inner walls of the termination trench. The first and second spacers are disposed on two sidewalls of the termination trench. The first doped region formed beneath the termination trench has a conductive type reverse to that of the epitaxial layer.

A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.