Horizontal Cavity Surface Emitting Lasers (HCSELs) with angled facets may be fabricated by a chemical or physical etching process, and the epitaxially grown semiconductor device layers may be transferred through a selective etch and release process from their original epitaxial substrate to a carrier wafer.

A switching includes a gallium nitride semiconductor and a gate insulation film. The gate insulation film is made of silicon oxide and disposed above the gallium nitride semiconductor layer. An interface between the gallium nitride insulation film and the gate insulation film is either free of a gallium oxide layer or provided with the gallium oxide layer with a thickness of 1 nanometer or smaller.

An integrated semiconductor device includes a silicon body that includes <111> single crystal silicon, a semiconductor device that is disposed within the silicon body, a III-nitride body disposed on the silicon body, and a III-nitride device that is disposed within the III-nitride body, wherein the semiconductor device is operatively coupled to the III-nitride device.

A method of forming a film can include heating a CVD reactor chamber containing a substrate to a temperature range between about 750 degrees Centigrade and about 950 degrees Centigrade, providing a first precursor comprising Al to the CVD reactor chamber in the temperature range, providing a second precursor comprising Sc to the CVD reactor chamber in the temperature range, providing a third precursor comprising nitrogen to the CVD reactor chamber in the temperature range, and forming the film comprising ScAlN on the substrate.

A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

A heterostructure, includes: a substrate; and a buffer layer that includes a plurality of layers having a composition Al.sub.xIn.sub.yGa.sub.1-x-yN, where x1 and y0; wherein the buffer layer has a first region that includes at least two layers, a second region that includes at least two layers, and a third region that includes at least two layers.

A high electron mobility transistor (HEMT) includes a semiconductor channel layer, a semiconductor barrier layer, a patterned semiconductor capping layer, and a patterned semiconductor protection layer disposed on a substrate in sequence. The HEMT further includes an interlayer dielectric layer and a gate electrode. The interlayer dielectric layer covers the patterned semiconductor capping layer and the patterned semiconductor protection layer, and includes a gate contact hole. The gate electrode is disposed in the gate contact hole and electrically coupled to the patterned semiconductor capping layer, where the patterned semiconductor protection layer is disposed between the gate electrode and the patterned semiconductor capping layer. The resistivity of the patterned semiconductor protection layer is between the resistivity of the patterned semiconductor capping layer and the resistivity of the interlayer dielectric layer.

A semiconductor device includes a III-V compound semiconductor layer, a III-V compound barrier layer, a gate trench, a p-type doped III-V compound layer, an insulation layer, and a gate electrode. The III-V compound barrier layer is disposed on the III-V compound semiconductor layer. The gate trench is disposed in the III-V compound barrier layer. The p-type doped III-V compound layer is disposed in the gate trench, and a top surface of the p-type doped III-V compound layer and a top surface of the III-V compound barrier layer are substantially coplanar. The insulation layer is disposed on the III-V compound barrier layer. The insulation layer includes an opening located corresponding to the gate trench in a vertical direction. A part of the p-type doped III-V compound layer is disposed on the insulation layer in the vertical direction. The gate electrode is disposed on the p-type doped III-V compound layer.

A semiconductor device for power amplification includes a substrate, a lower electrode, a semiconductor layer, a source electrode, a drain electrode, a gate electrode, and a field plate. The semiconductor layer is divided into an active region and an isolation region. In a plan view, a channel region includes unit channel regions that are separated by the isolation region and arranged in a Y-axis direction. The source electrode includes unit source electrodes each of which faces a corresponding one of the unit channel regions. The field plate includes unit plates each of which faces a corresponding one of the unit channel regions. At least one of plate drive lines is provided, for each of the unit plates, within the isolation region, the plate drive lines extending in an X-axis direction and electrically connecting the unit source electrodes and the unit plates.

Integrated circuit structures and methods for a high precision die-to-wafer bonding technology for fabricating 3-D stacked IC dies. Embodiments include precise alignment structures and methods, and also provide fast fabrication techniques using simultaneous multi-die picking and placing of individual dies from a die-source wafer onto a recipient wafer. Stacked-die yields are improved over wafer-to-wafer bonding technologies by enabling testing and selection of known-good die-source dies before bonding onto the recipient wafer, and by providing optional physical alignment structures on the recipient wafer and/or die-source wafer. Embodiments enable, for example, fabrication of high-power, high-performance devices on ICs formed on GaAs or GaN die-source wafers and bonding individual die-source IC dies to ICs that include CMOS control and driver circuitry formed on an SOI recipient wafer. The resulting 3-D stacked IC dies may offer advantages that include scalability, reliability, and form-factor reduction.