Some embodiments relate to an integrated device, including a semiconductor film accommodating a two-dimensional carrier gas (2DCG) over a substrate; a first source/drain electrode over the semiconductor film; a second source/drain electrode over the semiconductor film; a semiconductor capping structure between the first source/drain electrode and the second source/drain electrode; a first gate overlying the semiconductor capping structure and between the first source/drain electrode and the second source/drain electrode in a first direction; a first helping gate overlying the semiconductor capping structure and bordering the first gate, wherein the first helping gate and the second source/drain electrode are arranged in a line extending in a second direction transverse to the first direction.

A semiconductor device includes a channel layer including a first group III-V semiconductor material; a barrier layer provided on an upper surface of the channel layer, the barrier layer including a second group III-V semiconductor material that is different than the first group III-V semiconductor material; a plurality of sources/drains spaced apart from each other on an upper surface of the barrier layer; a gate insulating layer covering the upper surface of the barrier layer and upper surfaces of the plurality of sources/drains; a gate provided on an upper surface of the gate insulating layer, the gate not overlapping the plurality of sources/drains; a plurality of source/drain electrodes electrically connected to corresponding sources/drains among the plurality of sources/drains; and a gate electrode electrically connected to the gate, wherein the plurality of source/drain electrodes has a diagonally symmetrical arrangement.

A technique for making contact to the cap layers in multifinger III-Nitride transistors with cap layers is described. A contact structure is disposed at an end of the transistor device and connects to the cap layer of individual fingers of the transistor device using a cap contact bus. A transistor is also described that includes a contact structure that is used to move the cap layer contact away from the individual fingers. Transistors may be created using unit cells, wherein each unit cell includes a contact structure and cap contact bus.

An HEMT includes: a heterostructure; a dielectric layer on the heterostructure; a gate electrode, which extends throughout the thickness of the dielectric layer; a source electrode; and a drain electrode. The dielectric layer extends between the gate electrode and the drain electrode and is absent between the gate electrode and the source electrode. In this way, the distance between the gate electrode and the source electrode can be designed in the absence of constraints due to a field plate that extends towards the source electrode.

A nitride semiconductor device, including a substrate with a first nitride semiconductor layer on its surface, a block layer, an electron transit layer and an electron supply layer sequentially formed thereon. Formed along an inner surface thereof a first opening penetrating through the block layer to the first nitride semiconductor layer, a source electrode provided in a second opening in a location away from the first opening and connected to the block layer. The second opening penetrating through the electron supply and electron transit layers to the block layer. On an opposite surface of the substrate a drain electrode is provided. Seen in plan view, the first opening and the source electrode extend in a same, longitudinal direction, and the first opening includes: two straight portions extending in the longitudinal direction with the source electrode being interposed therebetween, and a first connection portion connecting ends of the two straight portions.

An N-polar III-N high-electron mobility transistor device can include a III-N channel layer over an N-face of a III-N backbarrier, wherein a compositional difference between the channel layer and the backbarrier causes a 2DEG channel to be induced in the III-N channel layer adjacent to the interface between the III-N channel layer and the backbarrier. The device can further include a p-type III-N layer over the III-N channel layer and a thick III-N cap layer over the p-type III-N layer. The III-N cap layer can cause an increase in the charge density of the 2DEG channel directly below the cap layer, and the p-type III-N layer can serve to prevent a parasitic 2DEG from forming in the III-N cap layer.

A semiconductor device includes: a gate electrode including a junction portion forming a Schottky junction with a barrier layer; a projecting portion including first and second gate field plates and projecting from the junction portion; and an insulating layer including first and second sidewalls. An angle formed between a highest position of a bottom surface of the first gate field plate and a main surface of a substrate, viewed from the first position, is a second elevation angle. An angle formed between an end on the drain electrode side of a lowest portion of a bottom surface of the second gate field plate and the main surface, viewed from the first position, is a third elevation angle. The second elevation angle is larger than the third elevation angle. The bottom surface of the second gate field plate includes an inclined surface where a distance from the barrier layer monotonically increases.

A method for manufacturing a HEMT device includes forming, on a heterostructure, a dielectric layer, forming a through opening through the dielectric layer, and forming a gate electrode in the through opening. Forming the gate electrode includes forming a sacrificial structure, depositing by evaporation a first gate metal layer layer, carrying out a lift-off of the sacrificial structure, depositing a second gate metal layer by sputtering, and depositing a third gate metal layer. The second gate metal layer layer forms a barrier against the diffusion of metal atoms towards the heterostructure.

A nitride semiconductor device includes a channel layer, a barrier layer made of Al.sub.xIn.sub.yGa.sub.1-x-yN (x>0, x+y1), an active region that has a layered structure including the channel layer and the barrier layer, an inactive region that is formed at the layered structure around the active region and that is a concave portion having a bottom portion that reaches the channel layer, a gate layer made of a nitride semiconductor selectively formed on the barrier layer in the active region, a gate electrode formed on the gate layer, a first insulating film that covers the gate electrode and that is in contact with the barrier layer in the active region, and a second insulating film that covers the first insulating film and that is in contact with the inactive region.

In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.