A wafer includes a substrate and at least one intermediate layer formed on a surface of the substrate. The at least one intermediate layer covers the surface of the substrate at least partially. An outer surface of the at least one intermediate layer is directed away from the surface of the substrate. The wafer further includes nanostructures grown on the outer surface of the at least one intermediate layer. The at least one intermediate layer is formed in such a way that positions of growth of the nanostructures are predetermined on the outer surface of the at least one intermediate layer. At least one nanostructure material of the nanostructures is assembled at the positions of growth of the nanostructures.

A method for forming a high electron mobility transistor is disclosed. A mesa structure having a channel layer and a barrier layer is formed on a substrate. The mesa structure has two first edges extending along a first direction and two second edges extending along a second direction. A passivation layer is formed on the substrate and the mesa structure. A first opening and a plurality of second openings connected to a bottom surface of the first opening are formed and through the passivation layer, the barrier layer and a portion of the channel layer. In a top view, the first opening exposes the two first edges of the mesa structure without exposing the two second edges of the mesa structure. A metal layer is formed in the first opening and the second openings thereby forming a contact structure.

In an embodiment, a semiconductor die includes a base substrate having a first major surface, a second major surface opposing the first major surface, and a material other than a Group III nitride. A Group III nitride layer arranged on the first major surface of the base substrate includes a Group III nitride device. A first metallization structure is arranged on the Group III nitride layer and a second metallization structure is arranged on the second major surface of the base layer. The second metallization structure includes an electrically insulating inorganic layer arranged directly on the second major surface.

The present invention relates to a structure of hybrid type AlGaN/GaN high electron mobility transistor (HEMT) Device, which comprises a silicon substrate structure, and both of a depletion-mode (D-mode) AlGaN/GaN HEMT and a p-GaN gate enhancement-mode (E-mode) AlGaN/GaN HEMT disposed on the silicon substrate structure. By connecting the depletion-mode (D-mode) AlGaN/GaN HEMT to the p-GaN gate structure of the p-GaN gate enhancement-mode (E-mode) AlGaN/GaN HEMT in device design, the p-GaN gate E-mode AlGaN/GaN HEMT may be protected under any gate voltage.

The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes: a substrate (120); a first nitride semiconductor layer (130) on the substrate (120); a second nitride semiconductor layer (140) on the first nitride semiconductor layer (130) and having a band gap greater than a band gap of the first semiconductor layer (130); a transistor (14) on the second nitride semiconductor layer (140); and a protection circuit (40) on the second nitride semiconductor layer (140), wherein the protection circuit (40) is configured to dispel electrons from a gate node of the transistor (14) when a voltage on the gate node exceeds a first threshold voltage.

A GaN-based High Electron Mobility Transistor (HEMT) having a multi-threshold voltage, a preparation method, and an application therefor are provided. The HEMT structure includes a channel layer and a barrier layer; a Two-dimensional Electron Gas (2DEG) is formed between the channel layer and the barrier layer; the barrier layer is at least provided with a first source area, a second source area, a first gate area, a second gate area, a first drain area, and a second drain area; the first source area, the first gate area, and the first drain area cooperate with each other, so as to form a first HEMT unit; the second source area, the second gate area, and the second drain area cooperate with each other, so as to form a second HEMT unit. that the HEMT may well meet application requirements of high and low threshold logic circuits.

The present invention provides a nitride semiconductor device, including: a silicon substrate; a first lateral transistor over a first region of the silicon substrate and including: a first nitride semiconductor layer formed over the silicon substrate; and a first gate electrode, a first source electrode and a first drain electrode formed over the first nitride semiconductor layer; a second lateral transistor over a second region of the silicon substrate and including: a second nitride semiconductor layer formed over the silicon substrate; and a second gate electrode, a second source electrode and a second drain electrode formed over the second nitride semiconductor layer; a first separation trench formed over a third region; a source/substrate connecting via hole formed over the third region; a first interlayer insulating layer formed over the first source electrode and the second source electrode; and a second interlayer insulating layer formed in the first separation trench.

An RF transistor amplifier circuit comprises a Group III nitride based RF transistor amplifier having a gate terminal, a Group III nitride based self-bias circuit that includes a first Group III nitride based depletion mode high electron mobility transistor, the Group III nitride based self-bias circuit configured to generate a bias voltage, and a Group III nitride based depletion mode differential amplifier that is configured to generate an inverted bias voltage from the bias voltage and to apply the inverted bias voltage to the gate terminal of the Group III nitride based RF transistor amplifier. The Group III nitride based RF transistor amplifier, the Group III nitride based self-bias circuit and the Group III nitride based depletion mode differential amplifier are all implemented in a single die.

The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a III-nitride layer, a gate, a connection structure, and a gate bus. The gate is disposed over the III-nitride layer. The connection structure is disposed over the gate. The gate bus extends substantially in parallel to the gate and disposed over the connection structure from a top view perspective. The gate bus is electrically connected to the gate through the connection structure.

The present disclosure generally relates to a semiconductor device having a doped region underlying a gate layer and in a barrier layer. In an example, a semiconductor device includes a channel layer, a barrier layer, and a gate layer. The channel layer is over a semiconductor substrate, and the barrier layer is over the channel layer. The gate layer is over the barrier layer, and the gate layer is doped with a dopant. A first region in the barrier layer overlies a channel region in the channel layer and underlies the gate layer. The first region has a first concentration of the dopant. A second region in the barrier layer is laterally disposed from the first region. The second region has a second concentration of the dopant that is less than the first concentration.