A GaN-based High Electron Mobility Transistor (HEMT) having a multi-threshold voltage, a preparation method, and an application therefor are provided. The HEMT structure includes a channel layer and a barrier layer; a Two-dimensional Electron Gas (2DEG) is formed between the channel layer and the barrier layer; the barrier layer is at least provided with a first source area, a second source area, a first gate area, a second gate area, a first drain area, and a second drain area; the first source area, the first gate area, and the first drain area cooperate with each other, so as to form a first HEMT unit; the second source area, the second gate area, and the second drain area cooperate with each other, so as to form a second HEMT unit. that the HEMT may well meet application requirements of high and low threshold logic circuits.

The present invention provides a nitride semiconductor device, including: a silicon substrate; a first lateral transistor over a first region of the silicon substrate and including: a first nitride semiconductor layer formed over the silicon substrate; and a first gate electrode, a first source electrode and a first drain electrode formed over the first nitride semiconductor layer; a second lateral transistor over a second region of the silicon substrate and including: a second nitride semiconductor layer formed over the silicon substrate; and a second gate electrode, a second source electrode and a second drain electrode formed over the second nitride semiconductor layer; a first separation trench formed over a third region; a source/substrate connecting via hole formed over the third region; a first interlayer insulating layer formed over the first source electrode and the second source electrode; and a second interlayer insulating layer formed in the first separation trench.

An integrated circuit (IC) includes a lower group III-N layer having a first composition over a substrate, and an upper group III-N layer having a different second composition over the lower group III-N layer. A gate electrode of a High Electron Mobility Transistor (HEMT) is located over the upper group III-N layer. First and second resistor contacts make a conductive connection to the lower group III-N layer. An unbiased group III-N cover layer is located on the upper group III-N layer in a resistor area including a high Rs 2-DEG resistor, where the unbiased group III-N cover layer is positioned between the first and second contacts.

A method includes: forming a dielectric fin protruding above a substrate; forming a channel layer over an upper surface of the dielectric fin and along first sidewalls of the dielectric fin, the channel layer including a low dimensional material; forming a gate structure over the channel layer; forming metal source/drain regions on opposing sides of the gate structure; forming a channel enhancement layer over the channel layer; and forming a passivation layer over the gate structure, the metal source/drain regions, and the channel enhancement layer.

The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a III-nitride layer, a gate, a connection structure, and a gate bus. The gate is disposed over the III-nitride layer. The connection structure is disposed over the gate. The gate bus extends substantially in parallel to the gate and disposed over the connection structure from a top view perspective. The gate bus is electrically connected to the gate through the connection structure.

The present disclosure provides a semiconductor structure and a forming method thereof. The semiconductor structure includes: a substrate and an epitaxial layer disposed on the substrate. At least a part of the epitaxial layer is doped with metal atoms, and the doping concentration of the metal atoms at the bottom surface of the epitaxial layer near the substrate is larger than 110.sup.17 atoms/cm.sup.3.

The present disclosure generally relates to a semiconductor device having a doped region underlying a gate layer and in a barrier layer. In an example, a semiconductor device includes a channel layer, a barrier layer, and a gate layer. The channel layer is over a semiconductor substrate, and the barrier layer is over the channel layer. The gate layer is over the barrier layer, and the gate layer is doped with a dopant. A first region in the barrier layer overlies a channel region in the channel layer and underlies the gate layer. The first region has a first concentration of the dopant. A second region in the barrier layer is laterally disposed from the first region. The second region has a second concentration of the dopant that is less than the first concentration.

A high electron mobility transistor includes a semiconductor channel layer and a semiconductor barrier layer disposed on a substrate in sequence. A source electrode and a drain electrode are disposed on the semiconductor channel layer. A semiconductor cap layer is disposed on the semiconductor barrier layer. A first dielectric layer is disposed over the source electrode, the semiconductor cap layer and the drain electrode. A first via passes through the first dielectric layer and is extended downward onto the semiconductor cap layer. A gate electrode is disposed on the first dielectric layer and in contact with the first via. A first field plate is disposed in the first dielectric layer. A second field plate is disposed on the first dielectric layer and in contact with the first field plate.

The present disclosure relates to semiconductor structures and, more particularly, to a high-electron-mobility transistor and methods of manufacture. The structure includes: a gate structure; a first field plate on a first side of the gate structure; and a second field plate on a second side of the gate structure, independent from the first field plate.

For manufacturing a semiconductor electronic device a wafer is provided which has a substrate layer of semiconductor material having a first portion and a second portion distinct from the first portion. An epitaxial region of a single semiconductor material is grown on the first portion of the substrate layer. An epitaxial multilayer having a heterostructure is grown on the second portion of the substrate layer. A first electronic component based on the single semiconductor material is formed from the epitaxial region and a second electronic component based on heterostructure is formed from the heterostructure. Forming a first electronic component comprises forming a plurality of doped regions in the epitaxial region, after the step of growing an epitaxial multilayer.