A Tunnel Field-Effect Transistor (TFET) is provided comprising a source-channel-drain structure of a semiconducting material. The source-channel-drain structure comprises a source region being n-type or p-type doped, a drain region oppositely doped than the source region and an intrinsic or lowly doped channel region situated between the source region and the drain region. The TFET further comprises a reference gate structure covering the channel region and a source-side gate structure aside of the reference gate structure wherein the work function and/or electrostatic potential of the source-side gate structure and the reference work function and/or electrostatic potential of the reference gate structure are selected for allowing the tunneling mechanism of the TFET device in operation to occur at the interface or interface region between the source-side gate structure and the reference gate structure in the channel region.

Tunneling field effect transistors and fabrication methods thereof are provided, which include: an integrated circuit device which includes a circuit input configured to receive an input voltage and a circuit output configured to deliver an output current. The integrated circuit also includes a circuit element having at least one tunneling field effect transistor (TFET). The circuit element connects the circuit input to the circuit output and is characterized by a V-shaped current-voltage diagram. The V-shaped current-voltage diagram describes the relationship between the input voltage of the circuit input and the output current of the circuit output.

A transistor includes a channel layer in which a plurality of graphene whose edge portions are terminated with modifying groups different from each other are bonded to each other; a gate electrode formed on the channel layer via a gate insulating film; and a source electrode and a drain electrode formed on the channel layer.

A tunneling field effect transistor for light detection, including a p-type region connected to a source terminal, a n-type region connected to a drain terminal, an intrinsic region located between the p-type region and the n-type region to form a P-I junction or an N-I junction with the n-type region or the p-type region, respectively, a first insulating layer and a first gate electrode, the first gate electrode covering a portion of the intrinsic region on one side, and a second insulating layer and a second gate electrode, the second insulating layer and the second gate electrode covering an entire other side of the intrinsic region opposite to the one side, wherein an area of the intrinsic region that is not covered by the first gate electrode forms a non-gated intrinsic area configured for light absorption.

A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.

The electrostatic protective device includes an insulator and a semiconductor layer. The semiconductor layer includes a device forming region and a device separating region. The device forming region includes a primary first conductive impurity diffused layer, a body region, a secondary first conductive impurity diffused layer, and a second conductive region that are arranged in order. The second conductive region includes a second conductive impurity diffused layer separated electrically from the body region. The device separating region includes a device separating layer that surrounds the device forming region. A gate electrode is further provided on the body region in the semiconductor layer with an insulating film interposed in between.

A fin tunnel field effect transistor includes a seed region and a first type region disposed above the seed region. The first type region includes a first doping. The fin tunnel field effect transistor includes a second type region disposed above the first type region. The second type region includes a second doping that is opposite the first doping. The fin tunnel field effect transistor includes a gate insulator disposed above the second type region and a gate electrode disposed above the gate insulator. A method for forming an example fin tunnel field effect transistor is provided.

The present disclosure relates to an intra-band tunnel FET, which has a symmetric FET that is able to provide for a high drive current. In some embodiments, the disclosed intra-band tunnel FET has a source region having a first doping type and a drain region having the first doping type. The source region and the drain region are separated by a channel region. A gate region may generate an electric field that varies the position of a valence band and/or a conduction band in the channel region. By controlling the position of the valence band and/or the conduction band of the channel region, quantum mechanical tunneling of charge carries between the conduction band in the source region and in the drain region or between the valence band in the source region and in the drain region can be controlled.

The present invention provides a semiconductor element that can be manufactured easily at a low cost, can obtain a high tunneling current, and has an excellent operating characteristic, a method for manufacturing the same, and a semiconductor integrated circuit including the semiconductor element. The semiconductor element of the present invention is characterized in that the whole or a part of a tunnel junction is constituted by a semiconductor region made of an indirect-transition semiconductor containing isoelectronic-trap-forming impurities.

Methods and apparatus for quantum point contacts. In an arrangement, a quantum point contact device includes at least one well region in a portion of a semiconductor substrate and doped to a first conductivity type; a gate structure disposed on a surface of the semiconductor substrate; the gate structure further comprising a quantum point contact formed in a constricted area, the constricted area having a width and a length arranged so that a maximum dimension is less than a predetermined distance equal to about 35 nanometers; a drain/source region in the well region doped to a second conductivity type opposite the first conductivity type; a source/drain region in the well region doped to the second conductivity type; a first and second lightly doped drain region in the at least one well region. Additional methods and apparatus are disclosed.