A Tunnel Field-Effect Transistor comprising a source-channel-drain structure, the source-channel-drain structure comprising a source region doped with a dopant element having a first dopant type and a first doping concentration; a drain region doped with a dopant element having a second dopant type opposite compared to the first dopant type, and a second doping concentration, a channel region situated between the source region and the drain region and having an intrinsic doping concentration, or lowly doped concentration being lower than the doping concentration of the source and drain regions, a gate stack comprising a gate electrode on a gate dielectric layer, the gate stack covering at least part of the channel region and extending at the source side up to at least an interface between the source region and the channel region, a drain extension region in the channel region or on top thereof, the drain extension region being formed from a material suitable for creating, and having a length/thickness ratio such that, in use, it creates a charged layer, in the OFF-state of the TFET, with a charge opposite to the charge of the majority carriers in the drain region.

The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO.sub.2 region.

A tunneling field-effect transistor may be provided that includes: a substrate; a source which is formed on the substrate and into which p+ type impurity ion is injected; a drain which is formed on the substrate and into which n+ type impurity ion is injected; a plurality of vertically stacked nanowire channels which are formed on the substrate; a gate insulation layer which is formed on the plurality of nanowire channels; and a gate which is formed on the gate insulation layer. As a result, it is possible to generate a higher driving current without changing the length of the gate and the area of the channel (degree of integration).

According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, an insulating region, and a third semiconductor region of the first conductivity type. The first semiconductor region is provided between the first electrode and the second electrode, and is in contact with the first electrode. The second semiconductor region is provided between the first semiconductor region and the second electrode. The second semiconductor region is in contact with the second electrode. The insulating region extends in a direction from the second electrode toward the first semiconductor region. The insulating region is in contact with the second electrode. The third semiconductor region is provided between the second semiconductor region and the insulating region.

A Tunnel Field-Effect Transistor (TFET) is provided comprising a source-channel-drain structure of a semiconducting material. The source-channel-drain structure comprises a source region being n-type or p-type doped, a drain region oppositely doped than the source region and an intrinsic or lowly doped channel region situated between the source region and the drain region. The TFET further comprises a reference gate structure covering the channel region and a source-side gate structure aside of the reference gate structure wherein the work function and/or electrostatic potential of the source-side gate structure and the reference work function and/or electrostatic potential of the reference gate structure are selected for allowing the tunneling mechanism of the TFET device in operation to occur at the interface or interface region between the source-side gate structure and the reference gate structure in the channel region.

A method of manufacturing a semiconductor device includes preparing a light ion source, a first mask and a second mask. A side of a first region on a top surface of a semiconductor substrate is shielded by using the first mask. The top surface, with the side of the first region thereon being shielded with the first mask, is irradiated with light ions by operating the light ion source to introduce lattice defects at a specified depth on a side of a second region on the top surface. A side of the second region on a bottom surface of the semiconductor substrate is shielded by using the second mask. The bottom surface, with the side of the second region thereon being shielded with the second mask, is irradiated with light ions by operating the light ion source to introduce lattice defects at a specified depth on the side of the first region on the bottom surface.

A semiconductor device and method of manufacturing a semiconductor device using a semiconductor fin is provided. In an embodiment the fin is formed from a substrate, a middle section of the fin is covered, and then portions of the fin on either side of the middle section are removed. A series of implants is then performed and a gate dielectric and a gate electrode are formed to form a tunneling field effect transistor from the fin.

A semiconductor memory device may include a pillar, a gate and at least one ferroelectric layer. The pillar may include a source, a drain and a channel region. The drain may be arranged over the source. The channel region may be arranged between the source and the drain. The gate may be formed on an outer surface of the pillar. The ferroelectric layer may be interposed between the pillar and the gate.

The present invention relates generally to integrated circuits and more particularly, to a structure and method of forming a hybrid circuit including a tunnel field-effect transistor (TFET) and a conventional field effect transistor (FET). Embodiments of the present invention include a hybrid amplifier which features a TFET common-source feeding a common-gate conventional FET (e.g. a MOSFET). A TFET gate may be electrically isolated from an output from a conventional FET. Thus, a high impedance input may be received by a TFET with a high-isolation output (i.e. low capacitance) at a conventional FET. A hybrid circuit amplifier including a TFET and a conventional FET may have a very high input impedance and a low miller capacitance.

A Tunnel Field-Effect Transistor comprising a source-channel-drain structure, the source-channel-drain structure comprising a source region doped with a dopant element having a first dopant type and a first doping concentration; a drain region doped with a dopant element having a second dopant type opposite compared to the first dopant type, and a second doping concentration, a channel region situated between the source region and the drain region and having an intrinsic doping concentration, or lowly doped concentration being lower than the doping concentration of the source and drain regions, a gate stack comprising a gate electrode on a gate dielectric layer, the gate stack covering at least part of the channel region and extending at the source side up to at least an interface between the source region and the channel region, a drain extension region in the channel region or on top thereof, the drain extension region being formed from a material suitable for creating, and having a length/thickness ratio such that, in use, it creates a charged layer, in the OFF-state of the TFET, with a charge opposite to the charge of the majority carriers in the drain region.