Semiconductor devices, FinFET devices and methods of forming the same are disclosed. In accordance with some embodiments, a semiconductor device includes a substrate, a first gate stack, a first dielectric layer, a shielding layer and a connector. The first gate stack is over a substrate. The first dielectric layer is aside the first gate stack, wherein the top surface of the first gate stack is lower than the top surface of the first dielectric layer such that a first recess is provided above the first gate stack. The shielding layer is on the surface of the first recess and extends onto the top surface of the first dielectric layer. The connector is through the shielding layer and is electrically connected to the first gate stack.

Semiconductor devices, FinFET devices and methods of forming the same are disclosed. In accordance with some embodiments, a semiconductor device includes a substrate, a first gate stack, a first dielectric layer, a shielding layer and a connector. The first gate stack is over a substrate. The first dielectric layer is aside the first gate stack, wherein the top surface of the first gate stack is lower than the top surface of the first dielectric layer such that a first recess is provided above the first gate stack. The shielding layer is on the surface of the first recess and extends onto the top surface of the first dielectric layer. The connector is through the shielding layer and is electrically connected to the first gate stack.

An integrated circuit device includes a first III-V compound layer, a second III-V compound layer over the first III-V compound layer, a gate dielectric over the second III-V compound layer, and a gate electrode over the gate dielectric. An anode electrode and a cathode electrode are formed on opposite sides of the gate electrode. The anode electrode is electrically connected to the gate electrode. The anode electrode, the cathode electrode, and the gate electrode form portions of a rectifier.

The present invention provides a method of forming an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.

Dummy gates are removed from a pre-metal layer to produce a first opening (with a first length) and a second opening (with a second length longer than the first length). Work function metal for a metal gate electrode is provided in the first and second openings. Tungsten is deposited to fill the first opening and conformally line the second opening, thus leaving a third opening. The thickness of the tungsten layer substantially equals the length of the first opening. The third opening is filled with an insulating material. The tungsten is then recessed in both the first and second openings using a dry etch to substantially a same depth from a top surface of the pre-metal layer to complete the metal gate electrode. Openings left following the recess operation are then filled with a dielectric material forming a cap on the gate stack which includes the metal gate electrode.

Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein. In an embodiment, the vertical tunnel FET is formed by forming a core over a first type substrate region, forming a second type channel shell around a circumference greater than a core circumference, forming a gate dielectric around a circumference greater than the core circumference, forming a gate electrode around a circumference greater than the core circumference, and forming a second type region over a portion of the second type channel shell, where the second type has a doping opposite a doping of the first type. In this manner, line tunneling is enabled, thus providing enhanced tunneling efficiency for a vertical tunnel FET.

A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.

A work function setting metal stack includes a configuration of layers including a high dielectric constant layer and a diffusion prevention layer formed on the high dielectric constant layer. An aluminum doped TiC layer has a thickness greater than 5 nm wherein the configuration of layers is employed between two regions as a diffusion barrier to prevent mass diffusion between the two regions.

Field effect diode structures utilize a junction structure that has an L-shape in cross-section (a fin extending from a planar portion). An anode is positioned at the top surface of the fin, and a cathode is positioned at the end surface of the planar portion. The perpendicularity of the fin and the planar portion cause the anode and cathode to be perpendicular to one another. A first gate insulator contacts the fin between the top surface and the planar portion. A first gate conductor contacts the first gate insulator, and the first gate insulator is between the first gate conductor and the surface of the fin. Additionally, a second gate insulator contacts the planar portion between the end surface and the fin. A second gate conductor contacts the second gate insulator, and the second gate insulator is between the second gate conductor and the surface of the planar portion.

A semiconductor device including a substrate includes a first region and a second region and first and second transistors in the first and second regions, respectively. The first transistor includes a first gate insulating layer on the substrate, a first lower TiN layer on and in contact with the first gate insulating layer, a first etch-stop layer on the first lower TiN layer and a first upper gate electrode on the first etch-stop layer. The second transistor includes a second gate insulating layer on the substrate, a second lower TiN layer on and in contact with the second gate insulating layer, a second etch-stop layer on the second lower TiN layer and a second upper gate electrode on the second etch-stop layer. A thickness of the first lower TiN layer is less than a thickness of the second lower TiN layer