A semiconductor device may include one or more transistor structures that include a plurality of source/drain regions and a gate structure between the source/drain regions. The semiconductor device may further include one or more dielectric layers between a source/drain contact structure and a gate structure of the one or more of the transistor structures. The one or more dielectric layers may be manufactured using on oxidation treatment process to tune the dielectric constant of the one or more dielectric layers. The dielectric constant of the one or more dielectric layers may be tuned to reduce the parasitic capacitance between the source/drain contact structure and the gate structure (which are conductive structures). In particular, the dielectric constant of the one or more spacer dielectric may be tuned using the oxidation treatment process to lower the as-deposited dielectric constant of the one or more dielectric layers.

A semiconductor device with a barrier layer between a gate structure and gate spacer layers, and a method of fabricating the same are disclosed. The a method includes forming a fin structure on a substrate, forming a polysilicon structure on the fin structure, performing a nitridation operation to form a barrier layer on the polysilicon structure and the fin structure, forming gate spacer layers on the barrier layer, forming a source/drain region in the fin structure and adjacent to the barrier layer, annealing the gate spacer layers, and replacing the polysilicon structure with a gate structure.

A method includes forming an epitaxial source/drain region in a substrate; forming a first inter-layer dielectric over the epitaxial source/drain region; forming a gate stack over the substrate and adjacent to the first inter-layer dielectric; forming a gate mask over the gate stack; forming a source/drain plug through the first inter-layer dielectric and electrically connected to the epitaxial source/drain region; depositing a dielectric layer over the gate mask and the first inter-layer dielectric, the dielectric layer having a different etch selectivity than the gate mask; forming a second inter-layer dielectric over the dielectric layer; etching an opening through the second inter-layer dielectric and the dielectric layer, the opening exposing the source/drain plug and the gate mask; and forming a conductive feature in the opening, the conductive feature being electrically connected to the source/drain plug.

Provided is a semiconductor device based on a cell architecture which includes: a 1.sup.st semiconductor cell; and a 2.sup.nd semiconductor cell which is connected to the 1.sup.st semiconductor cell in a 1.sup.st direction such that an output pin of the 1.sup.st semiconductor cell is connected to an input pin of the 2.sup.nd semiconductor cell, wherein the 2.sup.nd semiconductor cell is in a form in which the 1.sup.st semiconductor cell is turned upside down.

An integrated circuit (IC) including a plurality of finfet cells designed with digital circuit design rules to provide smaller finfet cells with decreased cell heights, and analog circuit cell structures including first finfet cells of the plurality of finfet cells and including at least one cut metal layer. The smaller finfet cells with decreased cell heights provide a first shorter metal track in one direction and the at least one cut metal layer provides a second shorter metal track in another direction to increase maximum electromigration currents in the integrated circuit.

A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate of the first region, a third gate structure and a fourth gate structure on the substrate of the second region, a first interlayer insulating film on the substrate of the first region and including a first lower interlayer insulating film and a first upper interlayer insulating film, a second interlayer insulating film on the substrate of the second region and including a second lower interlayer insulating film and a second upper interlayer insulating film, a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, and a second contact formed between the third gate structure and the fourth gate structure and within the second interlayer insulating film.

A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.

Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess.

An integrated circuits (IC) includes a standard cell array and a SRAM cell array. The standard cell array includes standard cells having first P-type transistors arranged in a first column of the standard cell array and a first fin structure shared by the first P-type transistors. The SRAM cell array includes SRAM cells having second P-type transistors arranged in a second column of the SRAM cell array and second fin structures arranged in the second column. Each of the second fin structures is shared by two adjacent second P-type transistors respectively disposed in two adjacent SRAM cells. A material of the first fin structure is different from a material of the second fin structures. A dimension of the first fin structure along the first column is greater than a dimension of each of the second fin structures along the second column.