A stack including an active layer, a gate dielectric, and a gate electrode is formed in a forward or in a reverse order, over a substrate. The active layer includes a front channel layer, a bulk semiconductor layer, and a back channel layer. The front channel layer is formed by depositing a layer stack that include at least one post-transition metal oxide layer, a zinc oxide layer, and at least one acceptor-type oxide layer. The zinc oxide layer or at least one post transition metal oxide layer contacts the gate dielectric, and the at least one acceptor-type oxide layer is most distal from the gate dielectric. The front channel layer provides enhanced channel conductivity, while the back channel layer provides suppressed channel conductivity.

A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface. A portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees.

Provided is a method to manufacture a liquid crystal display device in which a contact hole for the electrical connection of the pixel electrode and one of the source and drain electrode of a transistor and a contact hole for the processing of a semiconductor layer are formed simultaneously. The method contributes to the reduction of a photography step. The transistor includes an oxide semiconductor layer where a channel formation region is formed.

A semiconductor device according to the present disclosure includes a fin structure over a substrate, a vertical stack of silicon nanostructures disposed over the fin structure, an isolation structure disposed around the fin structure, a germanium-containing interfacial layer wrapping around each of the vertical stack of silicon nanostructures, a gate dielectric layer wrapping around the germanium-containing interfacial layer, and a gate electrode layer wrapping around the gate dielectric layer.

Thermal stability of a transistor is improved in different ways. An interfacial layer between a source/drain electrode and a semiconductor layer is formed from a material having a higher bond dissociation energy than indium oxide. Alternatively, the interfacial layer is formed from a metal-doped oxide semiconductor material. As another option, a metal layer or a metal oxide layer is formed between the source/drain electrode and the interfacial layer.

A semiconductor device includes a fin-type active region that extends in length in a first horizontal direction on a substrate, a horizontal semiconductor layer on the fin-type active region, a seed layer on the fin-type active region and in contact with the horizontal semiconductor layer, a gate line that surrounds the horizontal semiconductor layer and the seed layer, on the fin-type active region, and that extends in length in a second horizontal direction that intersects the first horizontal direction, and a pair of vertical semiconductor layers respectively on first and second sides of the horizontal semiconductor layer in the first horizontal direction, on the fin-type active region, with the horizontal semiconductor layer therebetween, wherein an inner wall of each of the first and second vertical semiconductor layers contacts the horizontal semiconductor layer, and upper or lower surfaces of the vertical semiconductor layers contact the seed layer.

Provided are a display device and a method for manufacturing the same. The display device includes: a connection source electrode and a connection drain electrode connected to a first source electrode a the first drain electrode, respectively by penetrating an isolation insulating layer and a second interlayer dielectric layer to enhance a characteristic of an element and reliability of the display device.

An active via is taught which comprises at least one via and at least one transistor which acts as a switch element. The resulting active via can be used with 1D, 2.5D or 3D chips to: control circuit elements; reduce EMI between vias; increase the density of vias; improve power and thermal efficiencies of chips; simplify power, data and other routing networks on chips; enable a higher level stacking of dies or layers in a chip while maintaining modularity; etc. A control strategy system can be provided to remove the supply of power to one or more regions of the chip when the regions are not in use and to supply power to those regions when the regions are in use, or to control input and output to regions of the chip. The active vias can be fabricated with Back or Front End Of Line processes.

Gate spacer that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a gate stack disposed over a semiconductor layer and a gate spacer disposed on a sidewall of the gate stack. A source/drain feature is disposed in the semiconductor layer and adjacent the gate spacer. A low-k contact etch stop layer is disposed on a top surface and a sidewall of the gate spacer and a portion of the gate spacer is disposed between the low-k contact etch stop layer and the semiconductor layer. A source/drain contact is disposed on the source/drain feature and adjacent the low-k contact etch stop layer.

A transistor device having fin structures, source and drain terminals, channel layers and a gate structure is provided. The fin structures are disposed on a material layer. The fin structures are arranged in parallel and extending in a first direction. The source and drain terminals are disposed on the fin structures and the material layer and cover opposite ends of the fin structures. The channel layers are disposed respectively on the fin structures, and each channel layer extends between the source and drain terminals on the same fin structure. The gate structure is disposed on the channel layers and across the fin structures. The gate structure extends in a second direction perpendicular to the first direction. The materials of the channel layers include a transition metal and a chalcogenide, the source and drain terminals include a metallic material, and the channel layers are covalently bonded with the source and drain terminals.