Patent classifications
H10D30/6713
Thin film transistor, display device, and method for manufacturing thin film transistor
Provided is an oxide semiconductor thin film transistor with low parasitic capacitance and high reliability. A thin film transistor includes a substrate, an oxide semiconductor layer including a channel region, a source region, and a drain region, a gate insulating film, and a gate electrode. The gate insulating film includes one layer or two layers, at least one of the layers of the gate insulating film is a patterned gate insulating film located at a position separated from the source electrode and the drain electrode. A length of a lower surface of the patterned gate insulating film in a channel length direction is greater than a length of a lower surface of the gate electrode in the channel length direction. The length of the lower surface of the patterned gate insulating film in the channel length direction is greater than a length of the channel region in the channel length direction. The source region and the drain region have a higher hydrogen concentration than the channel region.
Vertical field effect transistors with metallic source/drain regions
Semiconductor devices having vertical FET (field effect transistor) devices with metallic source/drain regions are provided, as well as methods for fabricating such vertical FET devices. For example, a semiconductor device includes a first source/drain region formed on a semiconductor substrate, a vertical semiconductor fin formed on the first source/drain region, a second source/drain region formed on an upper surface of the vertical semiconductor fin, a gate structure formed on a sidewall surface of the vertical semiconductor fin, and an insulating material that encapsulates the vertical semiconductor fin and the gate structure. The first source/drain region comprises a metallic layer and at least a first epitaxial semiconductor layer. For example, the metallic layer of the first source/drain region comprises a metal-semiconductor alloy such as silicide.
Transistors and Methods of Forming Transistors
Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. First channel material is between the gate and the source region. The first channel material is spaced from the gate by one or more insulative materials. Second channel material is between the first channel material and the source region, and directly contacts the source region. The first and second channel materials are transition metal chalcogenide. One of the source and drain regions is a hole reservoir region and the other is an electron reservoir region. Tunnel dielectric material may be between the first and second channel materials.
Method for manufacturing semiconductor device
It is an object to provide a highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics. It is another object to manufacture a highly reliable semiconductor device at lower cost with high productivity. In a method for manufacturing a semiconductor device which includes a thin film transistor where a semiconductor layer including a channel formation region using an oxide semiconductor layer, a source region, and a drain region are formed using an oxide semiconductor layer, heat treatment for reducing impurities such as moisture (heat treatment for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor layer.
Method for fabricating a nanowire semiconductor transistor having an auto-aligned gate and spacers
Method of making a transistor with semiconducting nanowires, including: making a semiconducting nanowire on a support, one portion of the nanowire being covered by a dummy gate, in which the dummy gate and the nanowire are surrounded by a dielectric layer, removing the dummy gate, forming a first space surrounded by first parts of the dielectric layer, making an ion implantation in a second part of the dielectric layer under said first portion, said first parts protecting third parts of the dielectric layer, etching said second part, forming a second space, making a gate in the spaces, and a dielectric portion on the gate and said first parts, making an ion implantation in fourth parts of the dielectric layer surrounding second portions of the nanowire, the dielectric portion protecting said first and third parts, etch said fourth parts.
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A transistor with stable electrical characteristics is provided. Provided is a method for manufacturing a semiconductor device that includes, over a substrate, an oxide semiconductor, a first conductor, a first insulator, a second insulator, and a third insulator. The oxide semiconductor is over the first insulator. The second insulator is over the oxide semiconductor. The third insulator is over the second insulator. The first conductor is over the third insulator. The oxide semiconductor has a first region and a second region. To form the first region, ion implantation into the oxide semiconductor is performed using the first conductor as a mask, and then hydrogen is added to the oxide semiconductor using the first conductor as a mask.
Array substrate and manufacturing method thereof, and display device
Embodiments of the present disclosure provide an array substrate and a manufacturing method thereof, and a display device. The array substrate includes a base substrate, a first electrode pattern, a second electrode pattern, and an active layer pattern disposed on the base substrate, a first electrode protection pattern coating the first electrode pattern, and a second electrode protection pattern coating the second electrode pattern. The active layer pattern is disposed between the first electrode pattern and the second electrode pattern. The first electrode protection pattern and the second electrode protection pattern are connected to two sides of the active layer pattern, respectively. The problem that, the active layer pattern cannot be connected to the first electrode pattern and the second electrode pattern due to the surface oxidation, when the first electrode pattern and the second electrode pattern adopt material with low resistance characteristic, is avoided, thus increasing the product yield.
VERTICAL TRANSISTOR FABRICATION AND DEVICES
A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess; epitaxially growing a second drain from the second bottom surface of a second recess formed in the substrate; growing a channel material epitaxially on the first drain and the second drain; forming troughs in the channel material to form one or more fin channels on the first drain and one or more fin channels on the second drain, wherein the troughs over the first drain extend to the surface of the first drain, and the troughs over the second drain extend to the surface of the second drain; forming a gate structure on each of the one or more fin channels; and growing sources on each of the fin channels associated with the first and second drains.
Semiconductor device and method for manufacturing the same
An object is to improve field effect mobility of a thin film transistor using an oxide semiconductor. Another object is to suppress increase in off current even in a thin film transistor with improved field effect mobility. In a thin film transistor using an oxide semiconductor layer, by forming a semiconductor layer having higher electrical conductivity and a smaller thickness than the oxide semiconductor layer between the oxide semiconductor layer and a gate insulating layer, field effect mobility of the thin film transistor can be improved, and increase in off current can be suppressed.
Array substrate and method of fabricating the same
A method of manufacturing an array substrate is discussed. The method includes forming a gate line on a substrate including a pixel region, forming a gate electrode on the substrate and connected to the gate line, and forming a gate insulating layer on the gate line and the gate electrode. The method further includes forming a data line on the gate insulating layer and crossing the gate line to define the pixel region, forming a source electrode and a drain electrode on the gate insulating layer and corresponding to the gate electrode, the source electrode connected to the data line and the drain electrode spaced apart from the source electrode, and forming an oxide semiconductor layer on top of the source and drain electrodes.