A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.

A super-steep switching device is provided. The super-steep switching device may include a substrate, a semiconductor channel on the substrate, a source electrode and a drain electrode, which are disposed on the semiconductor channel and spaced apart from each other, a gate electrode overlapping a portion of the semiconductor channel and not overlapping a remaining portion of the semiconductor channel, and an insulating layer disposed between the gate electrode and the semiconductor channel and covering an entire surface of the semiconductor channel.

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.

An integrated circuits (IC) includes a standard cell array and a SRAM cell array. The standard cell array includes standard cells having first P-type transistors arranged in a first column of the standard cell array and a first fin structure shared by the first P-type transistors. The SRAM cell array includes SRAM cells having second P-type transistors arranged in a second column of the SRAM cell array and second fin structures arranged in the second column. Each of the second fin structures is shared by two adjacent second P-type transistors respectively disposed in two adjacent SRAM cells. A material of the first fin structure is different from a material of the second fin structures. A dimension of the first fin structure along the first column is greater than a dimension of each of the second fin structures along the second column.

A semiconductor device may include a substrate including first and second active regions and a field region therebetween, first and second active patterns respectively provided on the first and second active regions, first and second source/drain patterns respectively provided on the first and second active patterns, a first channel pattern between the first source/drain patterns and a second channel pattern between the second source/drain patterns, and a gate electrode extended from the first channel pattern to the second channel pattern to cross the field region. Each of the first and second channel patterns may include semiconductor patterns, which are stacked to be spaced apart from each other. A width of a lower portion of the gate electrode on the field region may decrease with decreasing distance from a top surface of the substrate.

A semiconductor device may include a substrate including first and second active regions and a field region therebetween, first and second active patterns respectively provided on the first and second active regions, first and second source/drain patterns respectively provided on the first and second active patterns, a first channel pattern between the first source/drain patterns and a second channel pattern between the second source/drain patterns, and a gate electrode extended from the first channel pattern to the second channel pattern to cross the field region. Each of the first and second channel patterns may include semiconductor patterns, which are stacked to be spaced apart from each other. A width of a lower portion of the gate electrode on the field region may decrease with decreasing distance from a top surface of the substrate.

A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.

A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.

A device including a first vertical field effect transistor having a first drain/source region and a second drain/source region, and a second vertical field effect transistor having a third drain/source region and a fourth drain/source region. The device including a first power contact situated on a frontside of the device and coupled to the first drain/source region, a second power contact situated on the frontside of the device and coupled to the third drain/source region, and a contact situated on a backside of the device and coupled to the second drain/source region and to the fourth drain/source region.

An integrated circuit is provided, including a first transistor of a first conductivity type comprising first and second active regions, a second transistor of a second conductivity type comprising third and fourth active regions and arranged under the first transistor along a first direction, a first gate structure extending in the first direction and shared by the first and second transistors, an isolation layer sandwiched between the first and second transistors and extending along a second direction to pass through the first gate structure, and a connection layer surrounded by the isolation layer and extending along the second direction to pass through the first gate structure. The isolation layer has a first surface contacting the first and second active regions and a second surface contacting the third and fourth active regions. The connection layer comprises first and second portions are electrically coupled to the first and fourth active regions.