A semiconductor structure, a system, and a method of forming a multi-silicide structure for stacked FETs within the semiconductor. The semiconductor structure may include an NFET. The semiconductor structure may also include a PFET. The semiconductor structure may also include an NFET silicide proximately connected to the NFET, where the NFET silicide is a first material. The semiconductor structure may also include a PFET silicide proximately connected to the PFET, where the PFET silicide is a second material different than the first material. The system may include the semiconductor structure. The method may include forming an NFET silicide proximately connected to an NFET, where the NFET silicide is a first material. The method may also include forming a PFET silicide proximately connected to a PFET, where the PFET silicide is a second material different than the first material.

A semiconductor device includes a first substrate having a first surface and a second opposite surface, a first lower interlayer insulating layer on the second surface, a first active pattern including a first lower pattern contacting the first surface, a plurality of first sheet patterns spaced apart from the first lower pattern in a second direction, a first gate structure on the first lower pattern, a first source/drain pattern on a side of the first gate structure, a second lower interlayer insulating layer including a third surface and a fourth opposite surface, a second active pattern including a second lower pattern contacting the third surface, a plurality of second sheet patterns spaced apart from the second lower pattern in the second direction, a second gate structure on the second lower pattern, wherein the first lower pattern has a first height, and the second lower pattern has a second different height.

A semiconductor device has a first region and a second region including a first structural layer, a second structural layer, first electrode structure and second electrode structure. The material of the first structural layer comprises monocrystalline diamond, and a portion of the first structural layer located in the first region is electrically isolated from a portion located in the second region. The second structural layer is disposed on the first structural layer, and located in the first region, and forms a heterojunction structure with the first structural layer; the material of the second structural layer includes a monocrystalline AlN film or a doped monocrystalline AlN film. The first electrode structure comprises a first source electrode, a first gate electrode and a first drain electrode. The second electrode structure comprises a second source electrode, a second gate electrode and a second drain electrode.

A multi-stack semiconductor device includes: a plurality of lower transistor structures arranged on a lower stack and including a plurality of lower fin structures surrounded by a plurality of lower gate structures, respectively; a plurality of upper transistor structures arranged on an upper stack and including a plurality of upper fin structures surrounded by a plurality of upper gate structures, respectively; and at least one of a lower diffusion break structure on the lower stack and a upper diffusion break structure on the upper stack, wherein the lower diffusion break structure is formed between two adjacent lower gate structures, and isolates two lower transistor structures respectively including the two adjacent lower gate structures from each other, and the upper diffusion break structure is formed between two adjacent upper gate structures, and isolates two upper transistor structures respectively including the two adjacent upper gate structures from each other.

A power amplifier module includes a power amplifier including a GaAs bipolar transistor having a collector, a base abutting the collector, and an emitter, the collector having a doping concentration of at least about 310.sup.16 cm.sup.3 at a junction with the base, the collector also having at least a first grading in which doping concentration increases away from the base; and an RF transmission line driven by the power amplifier, the RF transmission line including a conductive layer and finish plating on the conductive layer, the finish plating including a gold layer, a palladium layer proximate the gold layer, and a diffusion barrier layer proximate the palladium layer, the diffusion barrier layer including nickel and having a thickness that is less than about the skin depth of nickel at 0.9 GHZ. Other embodiments of the module are provided along with related methods and components thereof.

There is provided a semiconductor device capable of improving electrical characteristics and integration density. The semiconductor device includes an active pattern protruding from a substrate, the active pattern including long sidewalls extending in a first direction and opposite to each other in a second direction, a lower epitaxial pattern on the substrate and covering a part of the active pattern, a gate electrode on the lower epitaxial pattern and extending along the long sidewalls of the active pattern, and an upper epitaxial pattern on the active pattern and connected to an upper surface of the active pattern. The active pattern includes short sidewalls connecting with the long sidewalls of the active pattern, and at least one of the short sidewalls of the active pattern has a curved surface.

A semiconductor structure includes a semiconductor substrate, a first source/drain portion, a second source/drain portion, a first metal contact, a second metal contact and a first conductive carbon layer. The first and second source/drain portions are formed over the semiconductor substrate, and are spaced apart from each other. The first source/drain portion has a conductivity type different from that of the second source/drain portion. The first and second metal contacts are respectively formed on the first and second source/drain portions. The first conductive carbon layer is formed between the first source/drain portion and the first metal contact.

A semiconductor device includes; an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern and including semiconductor patterns spaced apart in a vertical stack, and a gate electrode extending across the channel pattern. The semiconductor patterns includes a first semiconductor pattern and a second semiconductor pattern. The gate electrode includes a first part between the substrate and the first semiconductor pattern and a second part between the first semiconductor pattern and the second semiconductor pattern. A width of the first part varies with a depth of the first part, such that a width of a middle portion of the first part is less than a width of a lower portion of the first part and a width of an upper portion of the first part.

Provided is a semiconductor structure with shared gated devices. The semiconductor structure comprises a substrate and a bottom dielectric isolation (BDI) layer on top of the substrate. The structure further comprises a pFET region that includes a p-doped Source-Drain epitaxy material and a first nanowire matrix above the BDI layer. The structure further comprises an nFET region that includes a n-doped Source-Drain epitaxy material and a second nanowire matrix above the BDI layer. The structure further comprises a conductive gate material on top of a portion of the first nanowire matrix and the second nanowire matrix. The structure further comprises a vertical dielectric pillar separating the pFET region and the nFET region. The vertical dielectric pillar extends downward through the BDI layer into the substrate. The vertical dielectric pillar further extends upward through the conductive gate material to a dielectric located above the gate region.

Provided is a semiconductor structure with shared gated devices. The semiconductor structure comprises a substrate and a bottom dielectric isolation (BDI) layer on top of the substrate. The structure further comprises a pFET region that includes a p-doped Source-Drain epitaxy material and a first nanowire matrix above the BDI layer. The structure further comprises an nFET region that includes a n-doped Source-Drain epitaxy material and a second nanowire matrix above the BDI layer. The structure further comprises a conductive gate material on top of a portion of the first nanowire matrix and the second nanowire matrix. The structure further comprises a vertical dielectric pillar separating the pFET region and the nFET region. The vertical dielectric pillar extends downward through the BDI layer into the substrate. The vertical dielectric pillar further extends upward through the conductive gate material to a dielectric located above the gate region.