A method includes forming an inductor die, which includes forming a metal via over a substrate, forming a magnetic shell encircling the metal via, with the metal via and the magnetic shell collectively forming an inductor, and depositing a dielectric layer around the magnetic shell. The method further includes placing the inductor die over a carrier, encapsulating the inductor die in an encapsulant, forming redistribution lines electrically connecting to the inductor, and bonding a device die to the redistribution lines. The device die is electrically coupled to the inductor through the redistribution lines.

A method includes forming an inductor die, which includes forming a metal via over a substrate, forming a magnetic shell encircling the metal via, with the metal via and the magnetic shell collectively forming an inductor, and depositing a dielectric layer around the magnetic shell. The method further includes placing the inductor die over a carrier, encapsulating the inductor die in an encapsulant, forming redistribution lines electrically connecting to the inductor, and bonding a device die to the redistribution lines. The device die is electrically coupled to the inductor through the redistribution lines.

A thin-film chip resistor-capacitor includes a substrate, a resistor layer, a dielectric layer, a thin-film capacitor layer, a first terminal electrode and a second terminal electrode. The resistor layer is disposed on the substrate. The dielectric layer is disposed on the resistor layer. The thin-film capacitor layer is disposed on the dielectric layer and includes first and second capacitor electrodes that are physically separated with respect to each other. The first terminal electrode is disposed on a first side edge of the substrate and is coupled to the resistor layer and the first capacitor electrode. The second terminal electrode is disposed on a second side edge of the substrate opposite to the first side edge and is coupled to the resistor layer and the second capacitor electrode.

A semiconductor device includes: a first chip mounting portion; a second chip mounting portion; a first semiconductor chip mounted on the first chip mounting portion; second and third semiconductor chips mounted on the second chip mounting portion; and a sealing body for sealing them. Here, the third semiconductor chip includes a first coil and a second coil that are magnetically coupled to each other. Also, the first coil is electrically connected with a first circuit formed in the first semiconductor chip, and the second coil is electrically connected with a second circuit formed in the second semiconductor chip. Also, in cross-sectional view, the second coil is located closer to the second chip mounting portion than the first coil. Further, a power consumption during an operation of the second semiconductor chip is greater than a power consumption during an operation of the first semiconductor chip.

A microelectronic device including an isolation device with a stabilized dielectric. The isolation device includes a lower isolation element, an upper isolation element, and an inorganic dielectric plateau between the lower isolation element and the upper isolation element. The dielectric sidewall of the inorganic dielectric plateau is stabilized in a nitrogen containing plasma which forms a SiO.sub.xN.sub.y surface on the dielectric sidewall of the inorganic dielectric plateau. The SiO.sub.xN.sub.y surface on the dielectric sidewall of the inorganic dielectric plateau reduces ingress of moisture into the dielectric stack of the inorganic dielectric plateau.

A microelectronic device including an isolation device with a stabilized dielectric. The isolation device includes a lower isolation element, an upper isolation element, and an inorganic dielectric plateau between the lower isolation element and the upper isolation element. The dielectric sidewall of the inorganic dielectric plateau is stabilized in a nitrogen containing plasma which forms a SiO.sub.xN.sub.y surface on the dielectric sidewall of the inorganic dielectric plateau. The SiO.sub.xN.sub.y surface on the dielectric sidewall of the inorganic dielectric plateau reduces ingress of moisture into the dielectric stack of the inorganic dielectric plateau.

To reduce the chip size of a chip-type electronic component including a capacitor and an inductor. A chip-type electronic component includes a capacitor constituted by a lower electrode pattern, an upper electrode pattern, and an insulating layer, an insulating layer covering the capacitor, and an inductor pattern disposed on the insulating layer. The inductor pattern has a section overlapping the capacitor, whereby an auxiliary capacitor is added. The inductor pattern is thus made to partly overlap the capacitor, so that a larger inductance can be obtained with a small chip size. In addition, characteristics can also be improved by auxiliary capacitance.

To reduce the chip size of a chip-type electronic component including a capacitor and an inductor. A chip-type electronic component includes a capacitor constituted by a lower electrode pattern, an upper electrode pattern, and an insulating layer, an insulating layer covering the capacitor, and an inductor pattern disposed on the insulating layer. The inductor pattern has a section overlapping the capacitor, whereby an auxiliary capacitor is added. The inductor pattern is thus made to partly overlap the capacitor, so that a larger inductance can be obtained with a small chip size. In addition, characteristics can also be improved by auxiliary capacitance.

An insulating transformer comprising: an insulation layer; a transformer including a first coil embedded in the insulation layer and a second coil; and a capacitor including a first capacitor electrode and a second capacitor electrode, the first capacitor electrode being arranged between the first coil and the second coil and connected to a first ground terminal, and the second capacitor electrode being arranged between the first capacitor electrode and the second coil and connected to a second ground terminal.

An insulating transformer comprising: an insulation layer; a transformer including a first coil embedded in the insulation layer and a second coil; and a capacitor including a first capacitor electrode and a second capacitor electrode, the first capacitor electrode being arranged between the first coil and the second coil and connected to a first ground terminal, and the second capacitor electrode being arranged between the first capacitor electrode and the second coil and connected to a second ground terminal.