A capacitor may include a substrate, a first capacitor portion disposed on the substrate, and a second capacitor portion disposed on the first capacitor portion. The first capacitor portion may include a first insulation layer having a plurality of trenches, a first electrode disposed on the first insulation layer and in the plurality of trenches, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.

A device comprises a destination substrate; a multilayer structure on the destination substrate, wherein the multilayer structure comprises a plurality of printed capacitors stacked on top of each other with an offset between each capacitor along at least one edge of the capacitors; and wherein each printed capacitor includes a plurality of electrically connected capacitors. Each printed capacitor of the plurality of printed capacitors can be a horizontal or a vertical capacitor. Each printed capacitor can include a plurality of capacitor layers, each capacitor layer including a plurality of electrically connected capacitors

[Object] To provide a photoelectric conversion film, a solid-state image sensor, and an electronic device which have an increased imaging characteristic.

[Solution] Provided is a photoelectric conversion film including: a subphthalocyanine derivative represented by the following General Formula (1),

##STR00001## where, in General Formula (1), X represents any substituent selected from among the group consisting of a halogen, a hydroxy group, a thiol group, an amino group, a substituted or unsubstituted alkoxy group, a substituted or unsubstituted aryloxy group, a substituted or unsubstituted alkyl group, a substituted or unsubstituted alkyl amine group, a substituted or unsubstituted aryl amine group, a substituted or unsubstituted alkylthio group and a substituted or unsubstituted arylthio group, R.sub.1 to R.sub.3 each independently represent a substituted or unsubstituted ring structure, and at least one of R.sub.1 to R.sub.3 includes at least one hetero atom in the ring structure.

A semiconductor device includes a substrate, a seed layer, a first patterned metal layer, a dielectric layer and a second metal layer. The seed layer is disposed on a surface of the substrate. The first patterned metal layer is disposed on the seed layer and has a first thickness. The first patterned metal layer includes a first part and a second part. The dielectric layer is disposed on the first part of the first patterned metal layer. The second metal layer is disposed on the dielectric layer and has a second thickness, where the first thickness is greater than the second thickness. The first part of the first patterned metal layer, the dielectric layer and the second metal layer form a capacitor. The first part of the first patterned metal layer is a lower electrode of the capacitor, and the second part of the first patterned metal layer is an inductor.

An ESD-protective-function-equipped composite electronic component is provided that includes multiple Zener diodes formed from first and second semiconductor layers. Moreover, the second semiconductor layers are disposed on an insulating substrate and in the same plane. The electronic component includes electrodes extending from each of the Zener diodes and one or more thin-film circuit element connected in series between a pair of the electrodes.

An integrated circuit has a semiconductor die provided in a first IC layer and an inductor fabricated on a second IC layer. The inductor may have a winding and a magnetic core, which are oriented to conduct magnetic flux in a direction parallel to a surface of a semiconductor die. The semiconductor die may have active circuit components fabricated in a first layer of the die, provided under the inductor layer. The integrated circuit may include a flux conductor provided on a side of the die opposite the first layer. PCB connections to active elements on the semiconductor die may progress through the inductor layer as necessary.

A sequence of semiconductor processing steps permits formation of both vertical and horizontal nanometer-scale serpentine resistors and parallel plate capacitors within a common structure. The method takes advantage of a CMP process non-uniformity in which the CMP polish rate of an insulating material varies according to a certain underlying topography. By establishing such topography underneath a layer of the insulating material, different film thicknesses of the insulator can be created in different areas by leveraging differential polish rates, thereby avoiding the use of a lithography mask. In one embodiment, a plurality of resistors and capacitors can be formed as a compact integrated structure within a common dielectric block, using a process that requires only two mask layers. The resistors and capacitors thus formed as a set of integrated circuit elements are suitable for use as microelectronic fuses and antifuses, respectively, to protect underlying microelectronic circuits.

An electronic component that includes a resistive element. A Ni concentration of a resistive thin film of the resistive element at a side where there is a connection interface with a connection electrode is higher than the concentration of Ni at the side opposite to the interface.

[Problem] There is demand for chip resistors that are compact and that have high resistivity. [Solution] A chip resistor (100) has a substrate (11), a first connection electrode (12) and a second connection electrode (13) that are formed on the substrate (11), and a resistor network that is formed on the substrate (11) and that has ends one of which is connected to the first connection electrode (12) and the other one of which is connected to the second connection electrode (13). The resistor network is provided with a resistive circuit. The resistive circuit has a resistive element film line (103) that is provided along inner wall surfaces of trenches (101). The resistive element film line (103) extending along the inner wall surfaces of the trenches (101) is long and has a high resistivity as a unit resistive element. [Effect] The resistivity of the chip resistor (100) as a whole can be increased.

High precision capacitors and methods for forming the same utilizing a precise and highly conformal deposition process for depositing an insulating layer on substrates of various roughness and composition. The method generally comprises the steps of depositing a first insulating layer on a metal substrate by atomic layer deposition (ALD); (b) forming a first capacitor electrode on the first insulating layer; and (c) forming a second insulating layer on the first insulating layer and on or adjacent to the first capacitor electrode. Embodiments provide an improved deposition process that produces a highly conformal insulating layer on a wide range of substrates, and thereby, an improved capacitor.