A device comprises a destination substrate; a multilayer structure on the destination substrate, wherein the multilayer structure comprises a plurality of printed capacitors stacked on top of each other with an offset between each capacitor along at least one edge of the capacitors; and wherein each printed capacitor includes a plurality of electrically connected capacitors. Each printed capacitor of the plurality of printed capacitors can be a horizontal or a vertical capacitor. Each printed capacitor can include a plurality of capacitor layers, each capacitor layer including a plurality of electrically connected capacitors

A semiconductor device includes a first semiconductor structure having a first active region pattern density. The semiconductor device further includes a second semiconductor structure having a second active region pattern density, wherein the second semiconductor structure comprises a first resistive element. The semiconductor device further includes a third semiconductor structure having a third active region pattern density, wherein the third semiconductor structure includes a second resistive element. The second semiconductor structure is adjacent to the first semiconductor structure and adjacent to the third semiconductor structure. The first semiconductor structure, the second semiconductor structure and the third semiconductor structure do not overlap.

A semiconductor device includes a package, an input terminal fixed to the package, an input pre-matched substrate provided in the package, a semiconductor element provided in the package and formed on a substrate different from the input pre-matched substrate, a matching circuit including a circuit element formed on the input pre-matched substrate, a first wire for connecting the input terminal and the circuit element, and a second wire for connecting the circuit element and the semiconductor element, a first MIM capacitor formed as part of the circuit element, and a first stabilization circuit formed as part of the circuit element to reduce oscillation, wherein a lower electrode of the first MIM capacitor is connected to the package through a via provided in the input pre-matched substrate.

Provided is a method of manufacturing a semiconductor device. The method of manufacturing the semiconductor device includes forming magneto tunnel layers, forming a hard mask on the magneto tunnel layers, etching the magneto tunnel layers to form a magneto tunnel junction, wherein etching by-products are formed on sidewalls of the magneto tunnel junction, performing chemical treatment on the etching by-products to convert the etching by-products into a chemical reactant; and inspecting the chemical reactant.

Provided is a two-dimensional large-area growth method for a chalcogen compound, the method including: depositing a film of a transition metal element or a Group V element on a substrate; thereafter, uniformly diffusing a vaporized chalcogen element, a vaporized chalcogen precursor compound or a chalcogen compound represented by MX.sub.2+ within the film; and, thereafter, forming a film of a chalcogen compound represented by MX.sub.2 by forming the chalcogen compound represented by MX.sub.2 through post-heating.

A short circuit detection apparatus includes a capacitor connected to a high potential side of a semiconductor switching device via a diode and a resistor connected in series, a short circuit determination circuit that detects a terminal voltage of one terminal of the capacitor, and determines that the semiconductor switching device has short-circuited when the terminal voltage is equal to or greater than a threshold voltage, and a voltage control circuit that is provided between another terminal of the capacitor and a low potential side of the semiconductor switching device, switches between a conduction and an interruption of the capacitor and the semiconductor switching device, and applies an offset voltage between the capacitor and the semiconductor switching device when conducting.

An integrated device comprises an electrically conductive substrate having an upper surface comprising a recess and a lower surface for contacting the device, a multi-layer stack provided on the upper surface of the substrate and lining the recess, and an electrically conductive layer for contacting the device provided on the multi-layer stack. The multi-layer stack comprises a first, a second, a third and a fourth dielectric layer. Immediately adjacent dielectric layers have different bandgaps to trap charge carriers at respective interfaces between the dielectric layers during operation of the device.

RC-network components that include a substrate and capacitor having a thin-film top electrode portion at a surface on one side of the substrate. The low ohmic semiconductor substrate is doped to contribute 5% or less to the resistance of the RC-network component. The resistance provided in series with the capacitor is controlled by providing a contact plate, spaced from the thin-film top electrode portion by an insulating layer, and a set of one or more bridging contacts passing through openings in the insulating layer. The bridging contacts electrically interconnect the thin-film top electrode portion and the contact plate. Different resistance values can be set by appropriate selection of the number of bridging contacts. The openings are elongated thereby reducing temperature concentration at their periphery. Correspondingly, the bridging contacts have an elongated cross-sectional shape.

A resistive random access memory may include a memory array and a periphery around the memory array. Decoders in the periphery may be coupled to address lines in the array by forming a metallization in the periphery and the array at the same time using the same metal deposition. The metallization may form row lines in the array.

Provided is a two-dimensional large-area growth method for a chalcogen compound, the method including: depositing a film of a transition metal element or a Group V element on a substrate; thereafter, uniformly diffusing a vaporized chalcogen element, a vaporized chalcogen precursor compound or a chalcogen compound represented by MX.sub.2+ within the film; and, thereafter, forming a film of a chalcogen compound represented by MX.sub.2 by forming the chalcogen compound represented by MX.sub.2 through post-heating.