A semiconductor structure comprises a semiconductor substrate, a first trench capacitor, and a second trench capacitor. The substrate has first trenches arranged in a first arrangement direction with each first trench extending in a first extension direction and second trenches arranged in a second arrangement direction with each second trench extending in a second extension direction. The first trench capacitor includes first capacitor segments disposed inside the first trenches. The second trench capacitor includes second capacitor segments disposed inside the second trenches. One first capacitor segment of the first capacitor segments has an extending length different from that of another first capacitor segment of the first capacitor segments, and one second capacitor segment of the second capacitor segments has an extending length different from that of another second capacitor segment of the second capacitor segments.

A semiconductor device includes: a filter circuit including: a resistor; a MOS capacitor; and a MOM capacitor stacked on at least one of the resistor or the MOS capacitor, wherein the following inequalities are satisfied:

Mc/+Mr

Mr{square root over (1/2ft)}[Math. 1] where ft denotes a cutoff frequency of the filter circuit, Mr denotes a resistor area of a resistor-provided region in which the resistor is provided, Mc denotes a MOS capacitor area of a MOS capacitor-provided region in which the MOS capacitor is provided, denotes a resistivity of the resistor, denotes a MOS capacitance rate of the MOS capacitor, and denotes a MOM capacitance rate of the MOM capacitor.

Disclosed are semiconductor packages and semiconductor devices. In one embodiment, a semiconductor package includes a package, a first integrated passive device, and a second integrated passive device. The first integrated passive device is disposed below the package. The second integrated passive device is disposed between the package and the first integrated passive device. The first integrated passive device is electrically connected to the package through the second integrated passive device.

An integrated circuit structure including a metal-insulator-metal (MIM) capacitor module and a thin-film resistor (TFR) module is provided. The MIM capacitor module includes a bottom electrode base formed in a lower metal layer, a bottom electrode formed in a dielectric region between the lower metal layer and an upper metal layer, an insulator formed over the bottom electrode, and a top electrode formed in the upper metal layer over the insulator. The bottom electrode includes a cup-shaped bottom electrode component and a bottom electrode fill component formed in an interior opening defined by the cup-shaped bottom electrode component. The TFR module includes a pair of metal heads formed in the dielectric region and a resistor element connected across the pair of metal heads. Each metal head includes a cup-shaped head component and a head fill component formed in an interior opening defined by the cup-shaped head component.

Disclosed are semiconductor packages and semiconductor devices. In one embodiment, a semiconductor package includes a package, a first integrated passive device, and a second integrated passive device. The first integrated passive device is disposed below the package. The second integrated passive device is disposed between the package and the first integrated passive device. The first integrated passive device is electrically connected to the package through the second integrated passive device.

A semiconductor device includes: an insulating layer formed on a semiconductor substrate; a first resistor embedded in the insulating layer; a second resistor embedded in the insulating layer and connected in series with the first resistor; and a first capacitor comprising: a first upper electrode formed on the insulating layer and electrically connected to one end of the first resistor; and a first lower electrode formed in the insulating layer and electrically connected to one end of the second resistor, wherein the first lower electrode is electrically connected to the second resistor and is electrically connected to a reference electrode formed on the insulating layer.

RC architectures are provided that include a substrate provided with a capacitor having a thin-film top electrode portion at a surface of the substrate on one side thereof. The resistance provided in series with the capacitor is controlled by providing a contact plate, spaced from the thin-film top electrode portion, and a set of plural bridging contacts extending between, and electrically interconnecting, the thin-film top electrode portion and the contact plate. Different resistance values can be set by appropriate selection of the number of bridging contacts. The capacitor can be a three-dimensional capacitor and contacts are then provided on respective first and second sides of the substrate, which face each other in the thickness direction of the substrate.

RC-network components that include a substrate having a capacitor with a thin-film top electrode portion at a surface at one side of the substrate. The low ohmic semiconductor substrate is doped to contribute 5% or less to the resistance of the RC-network component. The resistance in series with the capacitor is controlled by providing a contact plate, spaced from the top electrode portion by an insulating layer, and a set of one or more bridging contacts in openings in the insulating layer. The bridging contacts electrically interconnect the top electrode portion and contact plate. Different resistance values can be set by appropriate selection of the number of bridging contacts. Temperature concentration at the periphery of the openings is reduced by providing reduced thickness portions in the insulating layer around the periphery of the openings.

Provided is a capacitor device, a unit synapse using the capacitor device, a synapse array using the unit synapses. The capacitor device comprises a semiconductor layer which include first and second doping regions formed to be spaced apart from each other and a body region formed between the first and second doping regions; a gate electrode provided above the body region; and a gate insulator stack to have a memory function and disposed between the gate electrode and the semiconductor layer. The capacitance between the gate electrode and the first doping region is determined according to information stored in the gate insulator stack, and the state of the capacitor device is determined according to the capacitance to be one of two preset states. The unit synapse comprises a pair of capacitor devices to perform an XNOR operation.