Integrated RC architecture, and methods of fabrication thereof

Abstract

RC architectures are provided that include a substrate provided with a capacitor having a thin-film top electrode portion at a surface of the substrate on one side thereof. The resistance provided in series with the capacitor is controlled by providing a contact plate, spaced from the thin-film top electrode portion, and a set of plural bridging contacts extending between, and electrically interconnecting, the thin-film top electrode portion and the contact plate. Different resistance values can be set by appropriate selection of the number of bridging contacts. The capacitor can be a three-dimensional capacitor and contacts are then provided on respective first and second sides of the substrate, which face each other in the thickness direction of the substrate.

Claims

1. An integrated RC component comprising: a substrate including a first surface on a first side and a second surface on a second side, the second side of the substrate opposite to the first side, the second side located below first side, wherein the first surface and the second surface are on separate flat planes, wherein the second surface is uniformly flat; a capacitor having a thin-film top electrode portion at the first surface on the first side of the substrate; an insulating layer arranged above the thin-film top electrode portion of the capacitor; a contact plate provided above and around the insulating layer; a set of plural bridging contacts traversing the insulating layer and electrically connecting the thin-film top electrode portion of the capacitor to the contact plate, the bridging contacts being evenly distributed across a surface of the thin-film top electrode portion of the capacitor in a grid formation; and first and second contacts arranged, respectively, on the first side of the substrate and on the second side of the substrate opposite to said first side, wherein the second contact is located below the second side and on the second surface of the substrate, wherein the first contact comprises the contact plate, and a series RC circuit is formed between the first and second contacts.

2. The RC component according to claim 1, wherein the substrate is a low ohmic semiconductor substrate doped to contribute no more than 5% to resistance of the RC component.

3. The RC component according to claim 1, wherein the bridging contacts are distributed evenly across the surface of the thin-film top electrode portion of the capacitor.

4. The RC component according to claim 2, wherein the capacitor is a 3D capacitor, the substrate is a low ohmic semiconductor substrate and a bottom electrode of the 3D capacitor is formed by the low ohmic semiconductor substrate.

5. The RC component according to claim 1, wherein the bridging contacts comprise a material having a conductivity greater than that of a material forming the top capacitor electrode.

6. The RC component according to claim 5, wherein the bridging contacts and the contact plate are integrally formed of a same material.

7. The RC component according to claim 1, wherein the capacitor is a 3D capacitor comprising a stack of MIM (metal-insulator-metal) layers formed in pores of a porous anodic oxide region in the substrate.

8. The RC component according to claim 1, wherein the thin-film top electrode portion of the capacitor comprises polysilicon.

9. The RC component according to claim 1, wherein, in a thickness direction of the thin-film top electrode portion of the capacitor, a length of the bridging contacts is greater than a thickness of the thin-film top electrode portion.

10. The RC component according to claim 1, wherein the top electrode portion of the capacitor has a square peripheral shape.

11. The RC component according to claim 1, wherein the contact plate and the top electrode portion of the capacitor have at least one of a same peripheral shape and a same size.

12. The RC component according to claim 1, wherein only a part of the capacitor top electrode to be located at the first surface on the first side of the substrate is a single planar sheet forming said thin-film top electrode portion.

13. A method of controlling a resistance of the RC component according to claim 1, the method comprising: acquiring a target value for the resistance of the RC component, and setting a number of bridging contacts dependent on the acquired target resistance value.

14. The method of claim 13, further comprising: acquiring a target current-handling capacity of the RC component; setting a cross-sectional area and a length of the bridging contacts based on the target current-handling capacity; and setting the number of bridging contacts based on the set cross-sectional area and length of the bridging contacts as well as on the acquired target resistance value.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Further features and advantages of the present invention will become apparent from the following description of certain embodiments thereof, given by way of illustration only, not limitation, with reference to the accompanying drawings in which:

(2) FIGS. 1A-1C illustrate a known monolithic component incorporating an RC architecture, in which FIG. 1A represents a cross-section through the component, FIG. 1B represents an equivalent circuit to the FIG. 1A structure, and FIG. 1C illustrates an arrangement for connecting the RC component to another device, on a mounting substrate;

(3) FIG. 2 is a diagram illustrating the effect of increasing the resistance of a device according to FIG. 1A by variation of the thickness of the substrate;

(4) FIGS. 3A-3C illustrate an RC architecture according to an embodiment of the present invention, in which FIG. 3A represents a cross-section through the architecture, FIG. 3B represents an equivalent circuit to the FIG. 3A structure, and FIG. 3C illustrates an arrangement for connecting a monolithic component incorporating the RC architecture of FIG. 3A to another device, on a mounting substrate;

(5) FIGS. 4A-4C illustrate how the equivalent series resistance at the top contact of the RC architecture of FIG. 3A component can be modulated by varying the number of bridging contacts between a thin-film top electrode portion of the capacitor and a contact plate;

(6) FIG. 5 is a flow diagram illustrating steps in an embodiment of a method of fabricating the RC architecture of FIG. 3;

(7) FIG. 6 shows a series of views illustrating the steps of FIG. 5;

(8) FIG. 7 is diagram illustrating an architecture according to another embodiment of the invention employing a 3D capacitor; and

(9) FIG. 8 is diagram illustrating an architecture according to an embodiment of the invention employing a planar capacitor.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

(10) An RC architecture according to a first embodiment of the invention, and an example method for fabricating the architecture, will now be described with reference to FIGS. 3-5. In the illustrated example the RC architecture is implemented as a monolithic RC component (IPD). However, in other embodiments of the invention the RC architecture may be integrated with other devices/circuits.

(11) As can be seen from FIG. 3A, the monolithic RC component 1 comprises a substrate 2. In the example illustrated by FIGS. 3 to 5, the substrate 2 is a low ohmic semiconductor substrate which defines the bottom electrode of a MIS structure constituting a three-dimensional (3D) capacitor. The 3D capacitor structure is formed over a set of holes which extend from the surface at a first side 2a of the substrate 2 into the bulk of the substrate. It will be understood that, in other embodiments, the 3D capacitor structure may make use of other texture provided in this surface of the substrate 2 (e.g. trenches, columns, . . . ).

(12) A continuous dielectric layer 4 is formed on the set of holes and conformally follows the contours of the surface, lining the walls of the holes. The dielectric layer 4 constitutes the dielectric of the 3D capacitor. The top electrode of the 3D capacitor is formed by a conductive material 6 which fills the holes and extends in a layer 7 at the surface of the substrate. A contact plate 9 is provided parallel to the layer 7 of the top capacitor electrode, separated by an insulating layer 10. The contact plate 9 may be used as one terminal (top terminal) of the RC component 1. In the illustrated example, the contact plate 9 and the layer 7 of the top capacitor electrode have the same surface area and peripheral shape. If desired, the contact plate 9 and the layer 7 of the top capacitor can have different surface areas from one another and/or different peripheral shapes from one another.

(13) A set of bridging contacts 8 are formed through the insulating layer and electrically interconnect the layer 7 of the 3D capacitor electrode and the contact plate 9. The locations of the bridging contacts 8 are distributed over the surface of the layer 7, as can be seen from FIG. 2C. Nine bridging contacts are represented in FIG. 2C. However, the number N of bridging contacts is set as a function of the target resistance of the RC component, as shall be explained below.

(14) A conductive layer 12 (backside metallization) is provided on the bottom surface of the substrate 2. The conductive layer 12 constitutes a bottom contact of the RC component 1.

(15) In the RC component 1 according to the embodiment of the invention represented in FIGS. 3A and 3B, the 3D capacitor structure extends through the substrate in the direction of the substrate's thickness, and opposing electrodes of the 3D capacitor are accessible at opposite sides 2a, 2b of the substrate 2. The resistance of the RC component depends on the contact structure at side 2a of the RC component, involving the contact plate 9 and the bridging contacts 8, but there may also be a resistance contribution from the bulk substrate 2. However, the contribution made by the substrate 2 may be reduced by employing a low ohmic substrate, in which case the equivalent circuit represented on the left-hand side of FIG. 3B tends towards the equivalent circuit illustrated at the right-hand side of FIG. 3B.

(16) For example, in a case where the sheet resistance is 100 Ohms per square, typically the substrate is n.sup.++ doped so that resistivity of the substrate is set from 1 mOhm.Math.cm to 5 mOhm.Math.cm. Thus, the substrate does not make a significant contribution to the overall resistance of the RC network. If the sheet resistance is increased (say, to 1 kOhm per square) then it is permissible to use a higher ohmic substrate, i.e. a substrate having a lower doping level. Preferably the doping of the substrate is set so that the substrate makes a contribution of no more than 5% (more preferably of the order of 1%) to the resistance of the RC network, while still ensuring that ohmic contact can be made with the backside metallization.

(17) The RC component 1 may be assembled and connected to a vertical power transistor (or other circuit) on a mounting substrate such as a DBC substrate in a comparable manner to that illustrated in FIG. 1C for the prior art device.

(18) As noted above, the choice of material for the semiconductor substrate 2 can affect the overall resistance of the RC architecture and this may reduce the controllability of the setting of the resistance value via the bridging contacts 8 and/or may deteriorate the temperature performance. Accordingly, to reduce the contribution which the substrate makes to the overall resistance, the substrate may be highly doped so as to be low ohmic. For example, N type silicon may be used having a doping level of the order of 10.sup.19 cm.sup.3. Semiconductor materials other than silicon may also be used, e.g. GaAs, with appropriate doping levels so that the substrate is low ohmic.

(19) The dielectric layer 4 may be made of a material (or stack of materials) such as SiO.sub.2, SiN, Al.sub.2O.sub.3, HfO.sub.2, etc.

(20) The conductive material 6 used to form the top capacitor electrode and the layer 7 may be polysilicon. In this case, because the final resistor in the architecture is defined by the sheet resistance of the polysilicon layer, the drift of the resistance value with temperature is the same as for a standard polysilicon process, and can be as low as a few 100 ppm/ C. Furthermore, the absolute accuracy of the resistance is the same as for a standard polysilicon process, i.e. the variation in nominal value in a batch of products can be <10%.

(21) It will be understood that conductive materials other than polysilicon may be used to form the top capacitor electrode, for example, TiN, Si/Ge, etc.

(22) The sheet resistance of the polysilicon top capacitor electrode can be adjusted by appropriate control of the doping of the material forming the top capacitor electrode. The sheet resistance of the top capacitor electrode can be adjusted in the same way in the case where this electrode is made of other semiconductor materials.

(23) The insulating layer 10 may be made of any convenient insulating material. An example material is SiO.sub.2 which is selected in view of its ubiquity and the fact that it enables an insulating layer having only moderate stress to be produced, but the invention is not limited to the use of this material. Other materials may be used, including materials such as SiN (assuming that increased stress is acceptable), and less common materials such as BCB (benzocyclobutene).

(24) The bridging contacts 8 may be made of any convenient conductive material. To avoid having a significant impact on the resistance of the finished component, it is advantageous for the bridging contacts to be made of a material having conductivity greater than that of the material forming the top capacitor electrode. In the case where the top capacitor electrode is made of polysilicon, an example material that may be used for the bridging contacts is aluminium (especially high purity aluminium having low granularity, which facilitates assembly), but the invention is not limited to use of this material.

(25) The contact plate 9 may be made of may be made of any convenient conductive material. In practice, the nature and dimensions of the plate 9 may be selected taking into account constraints that derive from the process (wire-bonding, ribbon bonding, etc.) that is used to assemble the RC component 1 with other components.

(26) In a case where the contact plate 9 is made of the same material as the bridging contacts 8, both elements may be formed in a common manufacturing process, which simplifies fabrication. Also, in a case where the contact plate 9 and bridging contacts 8 are made of the same material there is an improved mechanical and electrical connection between them. The latter property is advantageous because a poor-quality contact to the underlying polysilicon could in itself introduce a contribution to the overall resistance of the component. The layer 12 may be made of one or more conductive layers, such as metals. As one example, the layer 12 may be made of a stack of Ti, Ni and Au (or Al) layers, with the Ti layer improving adhesion to the semiconductor substrate, Ni serving as a barrier layer and Au (or Al) providing good solderability of the component.

(27) FIG. 4 shows a set of diagrams (FIGS. 4A-4C) to assist an explanation of how the use of the contact structure involving the contact plate 9 and the set of bridging contacts 8 enables the resistance of the RC architecture to be set. In FIGS. 4A-4C it is assumed that the capacitor-electrode portion 7 has a square peripheral shape.

(28) When the electrical properties of a thin film or plate of material are discussed it is common to refer to the sheet resistance of the film/plate. As is well known, the sheet resistance of a material is a quantity that is quoted in Ohms per square, and the electrical resistance of a sheet of a specific material is calculated according to the following relation:

(29) $R=R_s\frac{L}{W}$
where R is the electrical resistance provided by the sheet, Rs is the sheet resistance of the material forming the sheet, L is the length of the sheet and W is the width of the sheet. Thus, it can be understood that, provided that different sheets of a specific material are all square (i.e. L/W=1), these sheets will all have the same electrical resistance, irrespective of whether the sheets are of the same size. The present invention exploits this property.

(30) FIG. 4A illustrates a simplified electrical model of the capacitor electrode portion 7 (made of resistive polysilicon), in which Rsq_poly represents the sheet resistance of this polysilicon thin film 7. Rsq_poly is a function of the resistivity of the material, and of its thickness.

(31) FIG. 4B then represents a very simplified electrical model of the case where the capacitor and a single metal contact are added to FIG. 4A. It can be understood that the resistive access to the capacitor (or equivalent series resistance, ESR) is a function of the sheet resistance of the polysilicon layer 7, i.e. ESR=f (Rsq_poly).

(32) However, if the number of contacts is increased to a number N, as illustrated by the simplified electrical model of FIG. 4C, the polysilicon thin film 7 is notionally sub-divided into N smaller polysilicon squares sheets each having the same resistance value. If the N contacts are then connected together by a very low resistive plate (metal plate), i.e. the contact plate 9, the N smaller polysilicon squares will be virtually connected in parallel. Accordingly, the ESR becomes a function of the sheet resistance of layer 7 divided by the number N of bridging contacts 8, i.e. ESR=f (Rsq_poly/N).

(33) Thus, the resistance of an RC architecture embodying the invention can be adjusted by varying the number N of bridging contacts interconnecting the contact plate 9 to the capacitor-electrode layer 7. This can be easily realized with 1 additional isolation layer (e.g. SiO.sub.2) between these two layers.

(34) The above analysis is applicable in cases where the top plate-shaped electrode 7 of the capacitor is a thin film, that is, the thickness of the top plate-shaped electrode 7 is much less that the length of the bridging contacts. Typically, in the present embodiment of the invention a thin film plate-shaped capacitor top electrode made of polysilicon is less than 1 micrometer thick.

(35) RC architectures embodying the present invention provide a number of advantages, such as: Ability to withstand high currents: the inrush current is vertically divided by the N contacts and then spreads horizontally in all directions in the portion of the capacitor-electrode layer 7 connected to each contact. Furthermore, there is a quasi-vertical current path in the thin capacitor-electrode layer 7. Small footprint: the surface area occupied by the architecture is small irrespective of the resistor value. Low thickness: the thickness of the architecture does not need to vary with the resistor value, and it can be as low as that of a power transistor (e.g. 50 m). No need for multiple substrate resistivities: the variety of resistance values can be achieved using just one value for wafer resistivity (preferably, highly doped). Low process overhead for resistor variability: the resistance value may be programmed simply by 1 mask modification (contact opening). Versatile wiring arrangements: wiring is possible on the 4 sides of the architecture. Low temperature drift of the resistance. Good absolute resistor accuracy. Standard processes can be used for backside metallization (in the case of using a highly-doped silicon substrate).

(36) The resistance value could also be changed by changing the dimensions (cross-sectional area, length) of the bridging contacts. However, typically the dimensions of the bridging contacts are set based on the desired current-handling capacity of the device, and then the resistance value is set by selecting an appropriate number of bridging contacts. Likewise, the resistance value could be changed by changing the dimensions of the contact plate 9. However, in general, the dimensions of the contact plate 9 are set in view of constraints relating to assembly.

(37) In principle the locations of the bridging contacts 8 could be distributed over the surface area of the thin-film top electrode 7 of the capacitor in an uneven manner. This would have only a small impact on the resistance value observed at low frequencies. However, at higher frequencies such an uneven distribution of the bridging contacts 8 could lead to unpredictable variation in the value of resistance. In contrast, consistent frequency behaviour is observed in the case where the bridging contacts 8 are provided at locations that are evenly distributed over the surface area of the thin-film top electrode of the capacitor. Thus, for example, the area of the top electrode may be notionally divided up into squares and bridging contacts 8 may be positioned, respectively, at the centers of the squares. However, other even distributions may be used, for example, the bridging contacts may be positioned on concentric circles, evenly spaced from each other.

(38) An example implementation of a method for fabricating an RC component 10 such as that of FIG. 3A will now be described with reference to the flow chart of FIG. 5 and the diagrams shown in FIG. 6.

(39) It is assumed that a suitably-prepared semiconductor substrate is provided at the start of the method illustrated by FIG. 5. This may be, for example, a low-ohmic (highly-doped) silicon wafer in which multiple RC architectures according to the invention will be fabricated simultaneously. For simplicity, the following description only discusses formation of a single RC architecture intended to be a standalone component. Conventional processes may be used to form the elements of the MIS capacitor structure.

(40) Texture (e.g. holes, trenches or columns) is created in a surface of the substrate 2 (step S501). The texture may be created, for example, using masking and etching processes. Diagram (a) of FIG. 6 represents the substrate after texture has been created in a surface thereof. Then the dielectric layer 4 is deposited so as to conformally coat the textured surface (step S502), for example by chemical vapour deposition, atomic layer deposition, etc. Diagram (b) of FIG. 6 represents the substrate after deposition of the dielectric layer 4.

(41) Next, the conductive material 6 is deposited over the dielectric layer 4 (step S503), for example by chemical vapour deposition process. The conductive material 6 may be deposited to conformally cover the dielectric layer and to extend in a layer (e.g. a thin film) 7 at the surface of the substrate. For example, the conductive material 6 may fill the holes that are lined by the dielectric layer and create a film or plate-shaped layer 7 at the surface of the substrate. Diagram (c) of FIG. 6 represents the substrate after deposition of the conductive material 6.

(42) An insulating layer 10 is then formed on the capacitor-electrode portion 7 (S504), for example by depositing a layer of SiO.sub.2 by a plasma enhanced chemical vapor deposition process, or any other convenient process. A patterning process may then be used (step S505) to create a set of N via holes in the insulating layer. Diagram (d) of FIG. 6 represents the structure after the insulating layer 10 has been formed and the via holes created. As explained above, the number N of via holes may be set dependent on the target resistance of the RC component. The patterning process may be performed in any convenient manner and may include the steps of depositing a photoresist layer on the insulating layer (e.g. by spin coating), exposing and developing the photoresist to form a mask defining locations where via holes are to be formed, etching the insulating layer through the mask and removing the remaining photoresist.

(43) Next, a number N of bridging contacts are formed in the via holes (S506), notably by filling the via holes with a conductive material. The conductive material may be deposited by any convenient process, e.g. sputtering, CVD, PVD, etc. A contact plate 9 is then formed on the insulating layer (S507), for example by PVD. The contact plate 9 is electrically connected to the capacitor-electrode portion 7 by the bridging contacts. Diagram (e) of FIG. 6 represents the structure after the bridging contacts and contact plate have been formed. Finally, the backside metallization 12 is formed on the surface of the substrate opposite to the surface upon which the contact plate 9 is formed (S508). Conventional processes may be used to create the backside metallization. Diagram (f) of FIG. 6 represents the structure after the backside metallization has been formed.

(44) Although FIG. 5 shows the formation of the bridging contacts 8 and the formation of the contact plate 9 as separate processes, it should be noted that these elements may all be formed in a common process.

(45) The above description relates to the case where the capacitor in the RC network is a 3D capacitor and a low ohmic substrate constitutes the bottom electrode of the capacitor. However, the invention is not limited having regard to the technology used to implement the capacitor.

(46) Thus, for example, in another embodiment of the invention, illustrated in FIG. 7, a 3D capacitor is made by depositing layers of a MIM (metal-insulator-metal) stack in the pores of a porous anodic oxide region 17 provided in a metal layer (not shown). The lower metal layer of the MIM stack is designated 13 in FIG. 7, the insulator layer is designated 14 and the top metal layer is designated 15.

(47) As an example, the metal layer may be an aluminium layer and the anodic oxide may be aluminium oxide made by anodization of a selected region in the aluminium layer. The pores of the anodic oxide region 17 may extend all the way through the metal layer so that the inside of each pore communicates with an underlying conductive layer 16. In certain implementations of the embodiment of FIG. 7, the conductive layer 16 and the overlying metal layer are formed on a substrate 19, before the anodization process is performed. To enable the bottom terminal of the RC architecture 11 to be provided at the bottom of the structure, a conductive layer 12, serving as the bottom contact, may be provided and electrical contact between the bottom electrode of the 3D capacitor is achieved via a conductor 18 passing through the substrate 19. If desired, lateral isolation bands (not shown), made of electrically-insulating material, may be provided through the conductive layer 16, and this facilitates the integration of additional components in the device, either to the left and/or right sides of the 3D capacitor illustrated in FIG. 7, or in additional layers above or below the illustrated structure.

(48) Further information regarding how to fabricate a 3D capacitor in the pores of a porous anodic oxide region, and regarding techniques for integration of additional components, may be found in EP 3 063 789.

(49) Although FIG. 7 illustrates a 3D capacitor incorporating a MIM stack it should be understood that additional insulator and conductor layers may be provided (i.e. the stack may be a MIMIM stack, MIMIMIM stack, etc.).

(50) As another example of variation in the design of the capacitor, FIG. 8 illustrates an embodiment of RC architecture 21 implementing the invention in which the capacitor is a planar capacitor having a bottom electrode 27 formed on the substrate 2, a dielectric layer 4a and a top electrode layer 10.

(51) The embodiments illustrated in FIGS. 7 and 8 make use of distributed bridging contacts 8 and a contact plate 9 so as to set the resistance of the overall RC network to a desired value, as in the embodiment of FIGS. 3-5.

(52) Finally, it is noted that although the present invention has been described above with reference to certain specific embodiments, it will be understood that the invention is not limited by the particularities of the specific embodiments. Numerous variations, modifications and developments may be made in the above-described embodiments as would be appreciated to one skilled in the art.

(53) It is to be understood that references in this text to directions and locations, such as top and bottom, merely refer to the directions that apply when architectures and components are oriented as illustrated in the accompanying drawings. Thus a surface which may be top in FIG. 2A would be closest to the ground if the component 1 were to be turned upside down from the illustrated orientation.