A semiconductor device includes a substrate, a channel layer, an insulating layer, source/drain contacts, a gate dielectric layer, and a gate electrode. The channel layer over the substrate and includes two dimensional (2D) material. The insulating layer is on the channel layer. The source/drain contacts are over the channel layer. The gate dielectric layer is over the insulating layer and the channel layer. The gate electrode is over the gate dielectric layer and between the source/drain contacts.

A semiconductor device and a method for fabricating the semiconductor device are provided. The semiconductor device includes a plurality of device units. The device units includes a first device unit, and the first device unit includes a substrate including two source/drain regions and a gate region disposed between the two source/drain regions; a gate electrode layer disposed on the gate region, and a top surface of the gate electrode layer is coplanar to top surfaces of the two source/drain regions; a first channel layer disposed on the gate electrode layer, wherein the first channel layer includes a 2D semiconductor material; two air spacers disposed below the first channel layer and between the gate region and the two source/drain regions, respectively.

A semiconductor device includes a channel on a substrate. The channel includes a 2-dimensional material. A gate insulating layer is on a first portion of the channel. A gate electrode is on a portion of the gate insulating layer. First and second contact patterns are on second portions of the channel, respectively. Each of the first and second contact patterns includes a 2-dimensional material having an intercalation material disposed therein. First and second source/drain electrodes are on the first and second contact patterns, respectively. Each of the first and second source/drain electrodes includes a metal.

A semiconductor device includes a semiconductor pattern protruding in a direction perpendicular to a top surface of a substrate and having an inner surface and an outer surface that stand opposite to each other in a first direction parallel to the top surface of the substrate, a gate dielectric layer covering the inner surface and the outer surface of the semiconductor pattern and extending onto a top surface of the semiconductor pattern, a gate electrode on the gate dielectric layer and covering the outer surface, the top surface, and the inner surface of the semiconductor pattern, and an auxiliary pattern between the gate dielectric layer and the inner surface of the semiconductor pattern. The outer surface of the semiconductor pattern is in contact with the gate dielectric layer. The inner surface of the semiconductor pattern is in contact with the auxiliary pattern.

Embodiments provide a transistor structure, a semiconductor structure and a fabrication method thereof. The method for fabricating a transistor structure includes: providing a substrate; forming a channel layer on an upper surface of the substrate, the channel layer including a two-dimensional layered transition metal material layer; forming a source and a drain on two opposite sides of the channel layer, respectively; forming a gate dielectric layer on the upper surface of the substrate, the gate dielectric layer covering the channel layer, the source, and the drain; and forming a gate on an upper surface of the gate dielectric layer, the gate being positioned at least directly above the channel layer.

The present application provides a logic gate device. The logic gate device includes a gate electrode, a gate insulating layer, a bottom electrode, a two-dimensional semiconductor layer, a first top electrode and a second electrode. The gate insulating layer is located on the gate electrode. The bottom electrode is located on the gate insulating layer. The two-dimensional semiconductor layer is located on the bottom electrode and simultaneously covers the gate insulating layer. The first top electrode and the second electrode are located on the two-dimensional semiconductor layer. The bottom electrode, the two-dimensional semiconductor layer and the gate insulating layer form an air gap, and the air gap is distributed at both sides of the bottom electrode. The gate electrode is configured to connect a gate voltage, and the first top electrode and the second top electrode are configured to connect a signal input terminal.

Disclosed are a negative transconductance device and a multi-valued memory device using the same. The negative transconductance includes a monolithic WSe.sub.2 semiconductor thin film; a first doped layer disposed on a first area of the WSe.sub.2 semiconductor thin film; a second doped layer disposed on a second area of the WSe.sub.2 semiconductor thin film so as to supply holes to the second area, wherein the second area is spaced apart from the first area; a first electrode electrically connected to the first area of the WSe.sub.2 semiconductor thin film; a second electrode electrically connected to the second area of the WSe.sub.2 semiconductor thin film; and a third electrode for applying a gate voltage to the first area and the second area of the WSe.sub.2 semiconductor thin film, and to a third area thereof located between the first and second areas.

Devices, transistor structures, systems, and techniques are described herein related to field effect transistors having one or more metal chalcogenide nanoribbons coupled to a source and a drain. Channel regions of the metal chalcogenide nanoribbons are coupled to a gate structure between the source and the drain. The metal chalcogenide nanoribbons are capped with a layer including an oxide of a metal or metalloid element, optionally doped with or including carbon.

A method of forming a semiconductor device comprises the following steps. A dielectric layer is formed over a substrate. Source/drain contact layers are formed in the dielectric layer. A 2D material layer is formed over the dielectric layer and the source/drain contact layers. An annealing process is performed to the 2D material layer. After performing the annealing process, a tellurization process is performed to the 2D material layer. A gate structure is formed over the 2D material layer.

According to embodiments of the present disclosure, two-dimensional (2D) materials may be used as nanosheet channels for multi-channel transistors. Nanosheet channels made two-dimensional (2D) materials can achieve the same drive current at smaller dimensions and/or fewer number of channels, therefore enable scaling down and/or boost derive current. Embodiments of the present disclosure also provide a solution of P-type and N-type balancing in a device without increasing footprint of the device.