A semiconductor device includes channel structures spaced apart in a vertical direction; lower/upper first gate insulation patterns contacting lower/upper surfaces of the channel structures; a gate electrode surrounding lower/upper surfaces and a sidewall of the channel structures; and source/drain layers at sides of the gate electrode, wherein the channel structures include first/second 2D material layers stacked in the vertical direction, the first 2D material layer includes a semiconducting TMD including a first transition metal and first chalcogen elements that are bonded at lower/upper sides of the first transition metal, the second 2D material layer includes a second transition metal and a second chalcogen element, the second chalcogen element being bonded at a lower side of the second transition metal, and the second transition metal included in the second 2D material layer is covalently or ionically bonded with an element of the upper first gate insulation pattern.

A method of fabricating a semiconductor device includes forming a semiconductor layer, the semiconductor layer including a two-dimensional semiconductor material, forming a sacrificial layer on the semiconductor layer, forming a metal contact layer on the sacrificial layer, and removing the sacrificial layer. After the sacrificial layer is removed, the semiconductor layer and the metal contact layer are bonded to each other through a van der Waals bond.

A semiconductor device includes a channel on a substrate. The channel includes a 2-dimensional material. A gate insulating layer is on a first portion of the channel. A gate electrode is on a portion of the gate insulating layer. First and second contact patterns are on second portions of the channel, respectively. Each of the first and second contact patterns includes a 2-dimensional material having an intercalation material disposed therein. First and second source/drain electrodes are on the first and second contact patterns, respectively. Each of the first and second source/drain electrodes includes a metal.

A memory device includes a transistor and a memory cell. The transistor includes a first gate electrode, a second gate electrode, a channel layer, and a gate dielectric layer. The second gate electrode is over the first gate electrode. The channel layer is located between the first gate electrode and the second gate electrode. The gate dielectric layer is located between the channel layer and the second gate electrode. The memory cell is sandwiched between the first gate electrode and the channel layer.

Disclosed is a semiconductor doping method, and the semiconductor doping method includes: forming a molybdenum disulfide (MoS.sub.2) layer on a substrate; sputtering and depositing an aluminum nitride (AlOxNy) thin film on a surface of the molybdenum disulfide (MoS.sub.2) layer; and injecting electrons into the molybdenum disulfide (MoS.sub.2) through the deposition of the aluminum nitride (AlOxNy) thin film.

The present disclosure relates to an integrated circuit. In one implementation, the integrated circuit may include a semiconductor substrate; at least one source region comprising a first doped semiconductor material; at least one drain region comprising a second doped semiconductor material; at least one gate formed between the at least one source region and the at least one drain region; and a nanosheet formed between the semiconductor substrate and the at least one gate. The nanosheet may be configured as a routing channel for the at least one gate and may have a first region having a first width and a second region having a second width. The first width may be smaller than the second width.

A transition metal dichalcogenide (TMD) transistor includes a substrate, an n-type two-dimensional (2D) TMD layer, a metal source electrode, a metal drain electrode, and a gate dielectric. The substrate has a top portion that is an insulating layer, and the n-type 2D TMD layer is on the insulating layer. The metal source electrode, the metal drain electrode, and the gate dielectric are on the n-type 2D TMD layer. The metal gate electrode is on top of the gate dielectric and is between the metal source electrode and the metal drain electrode.