Embodiments disclose a semiconductor structure and a method for fabricating the same. The semiconductor structure includes: a substrate, a gate dielectric layer, a first conductive layer, and a conductive plug. The gate dielectric layer is provided on the substrate, and the first conductive layer is provided on the gate dielectric layer. The conductive plug is provided on the gate dielectric layer and covers a side wall of the first conductive layer, where a projection of the conductive plug on the substrate and a projection of the gate dielectric layer on the substrate at least partially overlap. By providing the conductive plug, a breakdown current can break down a region of the gate dielectric layer corresponding to the conductive plug by means of the conductive plug. That is, a breakdown position is adjusted by controlling an overlapping position between the conductive plug and the gate dielectric layer.

A memory device includes a transistor and a memory cell. The transistor includes a first gate electrode, a second gate electrode, a channel layer, and a gate dielectric layer. The second gate electrode is over the first gate electrode. The channel layer is located between the first gate electrode and the second gate electrode. The gate dielectric layer is located between the channel layer and the second gate electrode. The memory cell is sandwiched between the first gate electrode and the channel layer.

The present disclosure relates to an integrated circuit. In one implementation, the integrated circuit may include a semiconductor substrate; at least one source region comprising a first doped semiconductor material; at least one drain region comprising a second doped semiconductor material; at least one gate formed between the at least one source region and the at least one drain region; and a nanosheet formed between the semiconductor substrate and the at least one gate. The nanosheet may be configured as a routing channel for the at least one gate and may have a first region having a first width and a second region having a second width. The first width may be smaller than the second width.

A transition metal dichalcogenide (TMD) transistor includes a substrate, an n-type two-dimensional (2D) TMD layer, a metal source electrode, a metal drain electrode, and a gate dielectric. The substrate has a top portion that is an insulating layer, and the n-type 2D TMD layer is on the insulating layer. The metal source electrode, the metal drain electrode, and the gate dielectric are on the n-type 2D TMD layer. The metal gate electrode is on top of the gate dielectric and is between the metal source electrode and the metal drain electrode.

Transistors, devices, systems, and methods are discussed related to transistors including 2D material channels and heterogeneous 2D materials on the 2D material channels and coupled to source and drain metals, and their fabrication. The 2D material channels of the transistor allow for gate length scaling, improved switching performance, and other advantages and the heterogeneous 2D materials improve contact resistance of the transistor devices.