Provided is a TFT array substrate, which increases the area of a drain electrode of a TFT within a light-shielding zone to have the drain electrode overlapping a portion of a horizontal projection of a common electrode, wherein the drain electrode and the common electrode constitute a first storage capacitor and a pixel electrode and the common electrode constitute a second storage capacitor. The pixel electrode and the drain electrode are electrically connected and thus are of the same potential. The first storage capacitor and the second storage capacitor are connected in parallel and collectively form a storage capacitor such that the storage capacitor has a capacity that is equal to the sum of capacities of the first storage capacitor and the second storage capacitor, whereby, without reducing aperture ratio, the capacity of the storage capacitor is increased, crosstalk and image sticking are alleviated, and product display quality is enhanced.

Disclosed are a manufacturing method of a dual gate TFT substrate and a structure thereof. The manufacturing method of a dual gate TFT substrate includes sequentially manufacturing a bottom gate, a first isolation layer, an island shaped semiconductor layer, and a second isolation layer on a substrate; then, depositing a second metal layer, and implementing a patterning process to the second metal layer with one mask to form a source, a drain and a top gate at the same time; and then, sequentially manufacturing a third isolation layer and a pixel electrode. It can promote the stability of the TFT, reduce the amount of the masks, and shorten the process flow, simplifying the manufacture process and diminishing the production cost. In the structure of the dual gate TFT substrate, the structure is simple, and the stability of the TFT is better, and easy to manufacture.

The present invention discloses a conductive structure, a method of manufacturing the conductive structure, and an array substrate. The method of manufacturing the conductive structure, comprising steps of: Forming a barrier metal film and a copper metal film in this order on a substrate, wherein the copper metal film being laminated on the barrier metal film; forming a preset photoresist pattern on the copper metal film; etching the barrier metal film and the copper metal film; oxidizing an exposed sidewall of the etched barrier metal film and an exposed sidewall of the etched copper metal film, so as to generate metal oxide layers on the exposed sidewall of the etched barrier metal film and the exposed sidewall of the etched copper metal film, respectively; and stripping off the photoresist pattern by means of a photoresist stripping liquid. In the method of manufacturing the conductive structure according to embodiments of the present invention, the exposed sidewall of the conductive structure is oxidized to generate a uniform metal oxidization layer on the exposed sidewall before removing the photoresist from the conductive structure by a wet stripping process. In this way, it can effectively prevent the interfaces between the copper metal film and the barrier metal film from being separated during performing the wet stripping process.

A semiconductor device includes plurality of fin structures extending in first direction on semiconductor substrate. Fin structure's lower portion is embedded in first insulating layer. First gate electrode and second gate electrode structures extend in second direction substantially perpendicular to first direction over of fin structures and first insulating layer. The first and second gate electrode structures are spaced apart and extend along line in same direction. First and second insulating sidewall spacers are arranged on opposing sides of first and second gate electrode structures. Each of first and second insulating sidewall spacers contiguously extend along second direction. A second insulating layer is in region between first and second gate electrode structures. The second insulating layer separates first and second gate electrode structures. A third insulating layer is in region between first and second gate electrode structures. The third insulating layer is formed of different material than second insulating layer.

A Liquid crystal display device and manufacturing method thereof are provided. According to an exemplary embodiment of the present disclosure, an LCD device includes: a first substrate including a display area and a non-display area disposed outside of the display area; a gate electrode disposed on the first substrate and including a first-layer gate electrode and a second-layer gate electrode disposed on the first-layer gate electrode; a pixel electrode disposed on the same layer as the first-layer gate electrode; a source electrode and a drain electrode disposed on the gate electrode to be spaced from each other; and a contact connecting the drain electrode and the pixel electrode and including a first-layer contact, which is disposed on the same layer as the pixel electrode, and a second-layer contact, which is disposed on the first-layer contact.

A liquid crystal display (LCD) device capable of preventing impurities from permeating into a channel area of a switching element, the LCD device including: a gate electrode above a substrate; a semiconductor layer which overlaps the gate electrode; a drain electrode and a source electrode which overlap the semiconductor layer; an ohmic contact layer between the semiconductor layer and the drain electrode and between the semiconductor layer and the source electrode; a pixel electrode which is connected to one of the drain electrode and the source electrode; and a gate insulating layer between the gate electrode and the semiconductor layer, the gate insulating layer comprising fluorine. A concentration of the fluorine is decreasing, as the fluorine of the gate insulating layer being more adjacent to the substrate.

According to one embodiment, a display device includes an insulating substrate, a first insulating film, a second insulating film, a third insulating film, a fourth insulating film, a fifth insulating film, a sixth insulating film, a color filter layer, a semiconductor layer disposed between the second insulating film and the third insulating film, and a gate electrode disposed between the third insulating film and the fourth insulating film, wherein the first, fourth, and sixth insulating films are formed of a silicon nitride, and the second, third, and fifth insulating films are formed of a silicon oxide.

A semiconductor device in which parasitic capacitance is reduced is provided. A first oxide insulating layer and a first oxide semiconductor layer are sequentially formed over a first insulating layer. A first conductive layer is formed over the first oxide semiconductor layer and etched to form a second conductive layer. The first oxide insulating layer and the first oxide semiconductor layer are etched with the second conductive layer as a mask to form a second oxide insulating layer and a second oxide semiconductor layer. A planarized insulating layer is formed over the first insulating layer and the second conductive layer. A second insulating layer, a source electrode layer, and a drain electrode layer are formed by etching the planarized insulating layer and the second conductive layer. A third oxide insulating layer, a gate insulating layer, and a gate electrode layer are formed over the second oxide semiconductor layer.

Provided is a TFT array substrate, which increases the area of a drain electrode of a TFT within a light-shielding zone to have the drain electrode overlapping a portion of a horizontal projection of a common electrode, wherein the drain electrode and the common electrode constitute a first storage capacitor and a pixel electrode and the common electrode constitute a second storage capacitor. The pixel electrode and the drain electrode are electrically connected and thus are of the same potential. The first storage capacitor and the second storage capacitor are connected in parallel and collectively form a storage capacitor such that the storage capacitor has a capacity that is equal to the sum of capacities of the first storage capacitor and the second storage capacitor, whereby, without reducing aperture ratio, the capacity of the storage capacitor is increased, crosstalk and image sticking are alleviated, and product display quality is enhanced.

The present invention discloses an array substrate and a manufacturing method thereof, and a display apparatus. The array substrate comprises a base substrate, and a thin film transistor, a color filter layer and a first passivation layer provided on the base substrate. The surface of the first electrode provided by the present invention is provided with a concave-convex structure that can scatter external incident light, so that incident light from outside is diffusely reflected, thereby avoiding excessive concentration of light and improving external visibility and recognizability of the displayed pictures.