A semiconductor device may include a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including semiconductor patterns vertically stacked to be spaced apart from each other, a gate electrode on the plurality of semiconductor patterns, a gate contact electrically connected to the gate electrode, a first metal layer on the gate contact, the first metal layer including a first conductive via and a first interconnection pattern on the first conductive via, a second metal layer on the first metal layer, the second metal layer including a second conductive via and a second interconnection pattern on the second conductive via, and a diffusion prevention pattern between the first interconnection pattern and the second conductive via. A level of a bottom surface of the diffusion prevention pattern may be lower than a level of the topmost surface of the first interconnection pattern.

A memory structure includes randomly accessible, channel-all-around ferroelectric memory transistors organized as horizontal NOR memory strings. The NOR memory strings are formed over a semiconductor substrate in multiple scalable memory stacks of thin-film ferroelectric memory transistors. The three-dimensional memory stacks are manufactured in a process that includes forming holes in a multi-layer film stack for forming local word line structures and slit trenches to divide the film stack into memory stacks including local word line structures formed therein. The memory structure of channel-all-around ferroelectric memory transistors enables a scalable construction for realizing a high density, high capacity memory device.

The invention allows stable fabrication of a TFT circuit board used in a display device and having thereon an oxide semiconductor TFT. A TFT circuit board includes a TFT that includes an oxide semiconductor. The TFT has a gate insulating film formed on part of the oxide semiconductor and a gate electrode formed on the gate insulating film. A portion of the oxide semiconductor that is covered with the gate electrode 104 and a portion of the oxide semiconductor that is not covered with the gate electrode are both covered with a first interlayer insulating film. The first interlayer insulating film is covered with a first film 106, and the first film is covered with a first AlO film.

A semiconductor device includes thin film transistors each having an oxide semiconductor. The oxide semiconductor has a channel region, a drain region, a source region, and low concentration regions which are lower in impurity concentration than the drain region and the source region. The low concentration regions are located between the channel region and the drain region, and between the channel region and the source region. Each of the thin film transistors has a gate insulating film on the channel region and the low concentration regions, an aluminum oxide film on a first part of the gate insulating film, the first part being located on the channel region, and a gate electrode on the aluminum oxide film and a second part of the gate insulating film, the second part being located on the low concentration regions.

A semiconductor device with favorable electrical characteristics is provided. A semiconductor device with high reliability is provided. A semiconductor device with stable electrical characteristics is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, a second insulating layer, and a conductive layer. The semiconductor layer, the second insulating layer, and the conductive layer are stacked in this order over the first insulating layer. The semiconductor layer contains indium and oxygen and has a composition falling within a range obtained by connecting first coordinates (1:0:0), second coordinates (2:1:0), third coordinates (14:7:1), fourth coordinates (7:2:2), fifth coordinates (14:4:21), sixth coordinates (2:0:3), and the first coordinates in this order with a straight line in a ternary diagram showing atomic ratios of indium to an element M and zinc. In addition, the element M is one or more of gallium, aluminum, yttrium, and tin.

A method of manufacturing, with high mass productivity, liquid crystal display devices having highly reliable thin film transistors with excellent electric characteristics is provided. In a liquid crystal display device having an inverted staggered thin film transistor, the inverted staggered thin film transistor is formed as follows: a gate insulating film is formed over a gate electrode; a microcrystalline semiconductor film which functions as a channel formation region is formed over the gate insulating film; a buffer layer is formed over the microcrystalline semiconductor film; a pair of source and drain regions are formed over the buffer layer; and a pair of source and drain electrodes are formed in contact with the source and drain regions so as to expose a part of the source and drain regions.

There is provided a thin film transistor comprises a substrate; a semiconductor layer disposed on the substrate and including a channel area, a first conductive area connected to one side of the channel area, and a second conductive area connected to the other side of the channel area; a gate insulating layer covering areas other than the first conductive area and the second conductive area in the semiconductor layer; a gate electrode disposed on the gate insulating layer and overlapping the channel area in a plan view; and a first electrode disposed on the gate insulating layer on the one side of the channel area and in contact with a portion of the first conductive area. A first edge of the first electrode facing the gate electrode obliquely intersects a first edge of the gate insulating layer in a plan view.

Embodiments of the disclosure relate to methods of depositing seam-free gapfill. In some embodiments, the gapfill consists of titanium nitride. The gapfill methods comprise forming a first layer and a second layer. The firs layer is formed without treatment or densification, while the second layer is formed with periodic treatment. The resulting gapfill in advantageously seam-free.

A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first transistor including a first oxide, a second transistor including a second oxide, and a third oxide. The first oxide includes a channel formation region of the first transistor. The second oxide includes a channel formation region of the second transistor. The third oxide contains the same material as the first oxide and the second oxide. The third oxide is separated from the first oxide and the second oxide. In a top view, the third oxide is positioned between the first oxide and the second oxide. The third oxide is placed in the same layer as the first oxide and the second oxide.

Provided is a semiconductor structure with shared gated devices. The semiconductor structure comprises a substrate and a bottom dielectric isolation (BDI) layer on top of the substrate. The structure further comprises a pFET region that includes a p-doped Source-Drain epitaxy material and a first nanowire matrix above the BDI layer. The structure further comprises an nFET region that includes a n-doped Source-Drain epitaxy material and a second nanowire matrix above the BDI layer. The structure further comprises a conductive gate material on top of a portion of the first nanowire matrix and the second nanowire matrix. The structure further comprises a vertical dielectric pillar separating the pFET region and the nFET region. The vertical dielectric pillar extends downward through the BDI layer into the substrate. The vertical dielectric pillar further extends upward through the conductive gate material to a dielectric located above the gate region.