A semiconductor device includes: an SiC substrate having a first surface and a second surface; a first conductivity type SiC layer disposed on the first surface side of the SiC substrate, and including a low level density region having Z.sub.1/2 level density of 110.sup.11 cm.sup.3 or less measured by deep level transient spectroscopy (DLTS); a second conductivity type SiC region disposed on a surface of the SiC layer; a first electrode disposed on the SiC region; and a second electrode disposed on the second surface side of the SiC substrate.

A semiconductor device may include a strain relaxed buffer layer provided on a substrate to contain silicon germanium, a semiconductor pattern provided on the strain relaxed buffer layer to include a source region, a drain region, and a channel region connecting the source region with the drain region, and a gate electrode enclosing the channel region and extending between the substrate and the channel region. The source and drain regions may contain germanium at a concentration of 30 at % or higher.

A method includes forming an initial strain relaxed buffer layer on a semiconductor substrate. A trench is formed within the initial strain relaxed buffer layer. An epitaxial deposition process is performed to form an in situ carbon-doped strain relaxed buffer layer in the trench. A channel semiconductor material is formed on the initial strain relaxed buffer layer and on the in situ carbon-doped strain relaxed buffer layer in the trench. A plurality of fin-formation trenches that extend into the initial strain relaxed buffer layer is formed so as to thereby form an NMOS fin including the channel semiconductor material and the in situ carbon-doped strain relaxed buffer layer and a PMOS fin including the channel semiconductor material and the initial strain relaxed buffer layer. A recessed layer of insulating material and gate structures are formed around the NMOS fin and the PMOS fin.

An integrated circuit device includes a substrate including a first region and a second region, a first transistor in the first region, the first transistor being an N-type transistor and including a first silicon-germanium layer on the substrate, and a first gate electrode on the first silicon-germanium layer, and a second transistor in the second region and including a second gate electrode, the second transistor not having a silicon-germanium layer between the substrate and the second gate electrode.

A method of fabricating a semiconductor device is provided as follows. A channel layer is formed on a strain relaxed buffer (SRB) layer. A first etching process is performed on the channel layer and the SRB layer to form a plurality of trenches. The trenches penetrate through the channel layer and into the SRB layer to a first depth. First liners are formed on first sidewalls of the trenches having the first depth. The first liners cover the first sidewalls. A second etching process is performed on the SRB layer exposed through the trenches. The second etching process is performed on the SRB layer using a gas etchant having etch selectivity with respect to the first liners so that after the performing of the second etching process, the first liners remain on the first sidewalls.

A semiconductor structure, including: a base substrate; an insulating layer on the base substrate, the insulating layer having a thickness between about 5 nm and about 100 nm; and an active layer comprising at least two pluralities of different volumes of semiconductor material comprising silicon, germanium, and/or silicon germanium, the active layer disposed over the insulating layer, the at least two pluralities of different volumes of semiconductor material comprising: a first plurality of volumes of semiconductor material having a tensile strain of at least about 0.6%; and a second plurality of volumes of semiconductor material having a compressive strain of at least about 0.6%. Also described is a method of preparing a semiconductor structure and a segmented strained silicon-on-insulator device.

A transistor comprises a first conductive contact, a heterogeneous channel comprising at least one oxide semiconductor material over the first conductive contact, a second conductive contact over the heterogeneous channel, and a gate electrode laterally neighboring the heterogeneous channel. A device, a method of forming a device, a memory device, and an electronic system are also described.

Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.

Various methods for fabricating non-planar integrated circuit devices, such as FinFET devices, are disclosed herein. An exemplary method includes forming a rib structure extending from a substrate; forming a two-dimensional material layer (including, for example, transition metal dichalcogenide or graphene) on the rib structure and the substrate; patterning the two-dimensional material layer, such that the two-dimensional material layer is disposed on at least one surface of the rib structure; and forming a gate on the two-dimensional material layer. In some implementations, a channel region, a source region, and a drain region are defined in the two-dimensional material layer. The channel region is disposed between the source region and the drain region, where the gate is disposed over the channel region. In some implementations, the patterning includes removing the two-dimensional material layer disposed on a top surface of the substrate and/or disposed on a top surface of the rib structure.

An integrated circuit product includes an NFET FinFET device having a first fin that is made entirely of a first semiconductor material and a PFET FinFET device that includes a second fin having an upper portion and a lower portion, wherein the lower portion is made of the first semiconductor material and the upper portion is made of a second semiconductor material that is different from the first semiconductor material. A silicon nitride liner is positioned on and in contact with the lower portion of the second fin, wherein the silicon nitride liner is not present on or adjacent to the upper portion of the second fin or on or adjacent to any portion of the first fin.