A method of forming a semiconductor device that may include etching source and drain portions of a fin structure of a first semiconductor material selectively to an underlying semiconductor layer of a second semiconductor material, and laterally etching undercut region in the semiconductor layer underlying the fin structure. The method may further include filling the undercut region with a first conductivity type semiconductor material, and forming a second conductivity type semiconductor material for a source region and a drain region on opposing sides of the channel region portion of the fin structure.

A finFET device includes an n-doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped source or drain extension is disposed. The n-doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer.

A semiconductor device includes a transistor configuration including first and second gate electrodes, each of the first and second gate electrodes having at least a bottom layer and an upper layer including polycrystalline silicon grains, wherein the first gate electrode is a nMOS gate electrode formed in an nMOS region of the transistor configuration, wherein the polycrystalline silicon grains included in the bottom layer of the first gate electrode have a greater particle diameter than the polycrystalline grains included in the upper layer of the second gate electrode.

A gate structure is formed across a single crystalline semiconductor fin. An amorphizing ion implantation is performed employing the gate structure as an implantation mask to amorphize surface portions of the semiconductor fin into inverted U-shaped amorphous semiconductor portions. A gate spacer is formed around the gate structure, and the inverted U-shaped amorphous semiconductor portions are etched selective to a single crystalline portion of the semiconductor fin and the gate structure. A pair of inverted U-shaped cavities is formed underneath the gate spacer and above the remaining portion of the semiconductor fin. A doped epitaxial semiconductor material is deposited by a selective epitaxy process to form doped epitaxial active regions that include self-aligned extension portions underlying the gate spacer.

Tunneling field-effect transistors including silicon, germanium or silicon germanium channels and III-N source regions are provided for low power operations. A broken-band heterojunction is formed by the source and channel regions of the transistors. Fabrication methods include selective anisotropic wet-etching of a silicon substrate followed by epitaxial deposition of III-N material and/or germanium implantation of the substrate followed by the epitaxial deposition of the III-N material.

A semiconductor device includes a first multi-channel active pattern, a field insulation layer disposed on the first multi-channel active pattern and including a first region and a second region, the first region having a top surface protruding from a top surface of the second region to a top surface of the first multi-channel active pattern, a first gate electrode crossing the first multi-channel active pattern, the first gate electrode being disposed on the field insulation layer, and a first source or drain disposed between the first gate electrode and the first region of the field insulation layer and including a first facet, the first facet being disposed adjacent to the first region of the field insulation layer at a point lower than the top surface of the first multi-channel active pattern.

A method of forming a finFET transistor device includes forming a crystalline, compressive strained silicon germanium (cSiGe) layer over a substrate; masking a first region of the cSiGe layer so as to expose a second region of the cSiGe layer; subjecting the exposed second region of the cSiGe layer to an implant process so as to amorphize a bottom portion thereof and transform the cSiGe layer in the second region to a relaxed SiGe (rSiGe) layer; performing an annealing process so as to recrystallize the rSiGe layer; epitaxially growing a tensile strained silicon layer on the rSiGe layer; and patterning fin structures in the tensile strained silicon layer and in the first region of the cSiGe layer.

A semiconductor device includes a substrate, a gate electrode on the substrate, an insulating layer on the gate electrode, first and second lower vias in the insulating layer, first and second lower metal lines provided on the insulating layer and respectively connected to the first and second lower vias, and first and second upper metal lines provided on and respectively connected to the first and second lower metal lines. When viewed in a plan view, the first lower via is overlapped with the second upper metal line, and the second lower via is overlapped with the first upper metal line.

A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000 C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure has a dielectric layer comprised of an oxide of a first semiconductor material, wherein a second (and compositionally different) semiconductor material is formed between the dielectric layer and the first semiconductor material. In another embodiment, a portion of the second semiconductor material is replaced with a third semiconductor material in order to impart uniaxial strain to the lattice structure of the second semiconductor material.