A method for manufacturing a silicon carbide epitaxial substrate which has a first surface which is a (000-1) C-face, a silicon carbide epitaxial layer located on the first surface of the silicon carbide substrate, and a line-shaped surface defect density on a top surface of the silicon carbide epitaxial layer is less than 1.0 cm.sup.2 and a stacking fault density is less than 1.2 cm.sup.2.

A semiconductor device includes a semiconductor substrate having an element region and a terminal region located around the element region. The terminal region includes multiple guard rings and multiple first diffusion regions. When the semiconductor substrate is viewed in a plan view, one of the first diffusion regions is arranged correspondingly to one of the guard rings, and each of the guard rings is located in corresponding one of the first diffusion regions. A width of each of the first diffusion regions is larger than a width of corresponding one of the guard rings.

On a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, a gate insulating film, gate electrodes, an interlayer insulating film, first electrodes, and a second electrode are formed. Each of the first electrodes are formed by depositing a lower Ni film, an Al film, and an upper Ni film and etching the films to be apart from the interlayer insulating film; sintering the lower Ni film by a heat treatment and thereby forming a Ni silicide film; depositing a Ti film, a TiN film, and an AlSi film; and etching the AlSi film.

Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed JFET includes a vertical channel region located in a mesa and a first channel control region located on a first side of the mesa. The first channel control region is at least one of a gate region and a first base region. The JEFT also includes a second base region located on a second side of the mesa and extending through the mesa to contact the vertical channel region. The vertical channel can be an implanted vertical channel. The vertical channel can be asymmetrically located in the mesa towards the first side of the mesa.

Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

In a semiconductor device, a source region is made of an epitaxial layer so as to reduce variation in thickness of a base region and variation in a threshold value. Outside of a cell part, a side surface of a gate trench is inclined relative to a normal direction to a main surface of a substrate, as compared with a side surface of a gate trench in the cell part that is provided by the epitaxial layer of the source region being in contact with the base region.

An integrated circuits (IC) includes a standard cell array and a SRAM cell array. The standard cell array includes standard cells having first P-type transistors arranged in a first column of the standard cell array and a first fin structure shared by the first P-type transistors. The SRAM cell array includes SRAM cells having second P-type transistors arranged in a second column of the SRAM cell array and second fin structures arranged in the second column. Each of the second fin structures is shared by two adjacent second P-type transistors respectively disposed in two adjacent SRAM cells. A material of the first fin structure is different from a material of the second fin structures. A dimension of the first fin structure along the first column is greater than a dimension of each of the second fin structures along the second column.

A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The second semiconductor region also includes a wide portion and a narrow portion over the wide portion, wherein the narrow portion is narrower than the wide portion. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.