A method for forming a semiconductor device comprises forming a fin in a bulk semiconductor substrate and depositing a first insulator layer over portions of the bulk semiconductor substrate adjacent to the fin. The method further includes removing portions of the first insulator layer to reduce a thickness of the first insulator layer and expose a sidewall of the fin. An etch stop layer is deposited on the first insulator layer. A gate stack is formed over a channel region of the fin and over portions of the etch stop layer. A portion of the bulk semiconductor substrate is removed to expose portions of the etch stop layer and the fin, and a second insulator layer is deposited over exposed portions of the fin and the etch stop layer.

A semiconductor device according to an embodiment includes a SiC layer having a first plane and a second plane, a gate insulating film provided on the first plane, a gate electrode provided on the gate insulating film, a first SiC region of a first conductivity type provided in the SiC layer, a second SiC region of a second conductivity type provided in the first SiC region, a third SiC region of the first conductivity type provided in the second SiC region, and a fourth SiC region of the first conductivity type provided between the second SiC region and the gate insulating film, the fourth SiC region interposed between the second SiC regions, and the fourth SiC region provided between the first SiC region and the third SiC region.

A semiconductor device having a voltage resistant structure in a first aspect of the present invention is provided, comprising a semiconductor substrate, a semiconductor layer on the semiconductor substrate, a front surface electrode above the semiconductor layer, a rear surface electrode below the semiconductor substrate, an extension section provided to a side surface of the semiconductor substrate, and a resistance section electrically connected to the front surface electrode and the rear surface electrode. The extension section may have a lower permittivity than the semiconductor substrate. The resistance section may be provided to at least one of the upper surface and the side surface of the extension section.

In one general aspect, an apparatus can include a silicon carbide (SiC) device can include a gate dielectric, a first doped region having a first conductivity type, a source, a body region of the first conductivity type, and a second doped region having a second conductivity type. The second doped region can have a first portion and a second portion. The first portion can be disposed between the first doped region and the body region and the second portion can be disposed between the first doped region and the gate dielectric. The first portion of the second doped region can have a width less than a width of the first doped region.

A method of forming a semiconductor includes a providing a termination trench and an active trench within a semiconductor layer. The active trench is configured to be at a shallower depth than the termination trench to provide a trench depth difference. The selected trench depth difference in combination with one or more of the dopant concentration of the semiconductor layer, the thickness of the semiconductor layer, active trench width to termination trench width, and/or dopant profile of the semiconductor layer provide a semiconductor device having improved performance characteristics.

A semiconductor device includes an isolation layer, first and second fin structures, a gate structure and a source/drain structure. The isolation layer is disposed over a substrate. The first and second fin structures are disposed over the substrate, and extend in a first direction in plan view. Upper portions of the first and second fin structures are exposed from the isolation layer. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction. The source/drain structure is formed on the upper portions of the first and second fin structures, which are not covered by the first gate structure and exposed from the isolation layer, and wraps side surfaces and a top surface of each of the exposed first and second fin structures. A void is formed between the source/drain structure and the isolation layer.

A power semiconductor device includes a silicon carbide substrate and at least a first layer or region formed above the substrate. The silicon carbide substrate has a pattern of pits formed thereon. The device further comprising an ohmic metal disposed at least in the pits to form low-resistance ohmic contacts.

A method of forming a semiconductor device that includes forming a germanium including material on source and drain region portions of a silicon containing fin structure, and annealing to drive germanium into the source and drain region portions of the fin structure. The alloyed portions of fin structures composed of silicon and germanium are then removed using a selective etch. After the alloyed portions of the fin structures are removed, epitaxial source and drain regions are formed on the remaining portions of the fin structure.

A method for manufacturing a semiconductor substrate may comprise irradiating a surface of a first semiconductor layer and a surface of a second semiconductor layer with one or more types of first impurity in a vacuum. The method may comprise bonding the surface of the first semiconductor layer and the surface of the second semiconductor layer to each other in the vacuum. The method may comprise applying heat treatment to the semiconductor substrate produced in the bonding. The first impurity may be an inert impurity that does not generate carriers in the first and second semiconductor layers. The heat treatment may be applied such that a width of an in-depth concentration profile of the first impurity contained in the first and second semiconductor layers is narrower after execution of the heat treatment than before the execution of the heat treatment.

A semiconductor device includes a substrate having an upper surface layer of a second conduction type formed at an upper surface side, a drift layer of a first conduction type formed under the upper surface layer, a buffer layer of the first conduction type formed under the drift layer, and a lower surface layer of the second conduction type formed under the buffer layer, the buffer layer includes a plurality of upper buffer layers provided apart from each other, and a plurality of lower buffer layers provided apart from each other between the plurality of upper buffer layers and the lower surface layer, wherein the plurality of upper buffer layers are formed so that average impurity concentrations in first sections each extending from the upper end of one of the upper buffer layers to the next lower buffer layer are unified as a first concentration.