A power semiconductor device (10) comprises a semiconductor body (11) which includes a first main surface (12) and a second main surface (13), a gate insulator (14) arranged at the first main surface (12), and a gate electrode (15) separated from the semiconductor body (11) by the gate insulator (14). The semiconductor body (11) comprises a drift layer (16) of a first conductivity type, a well layer (27) of a second conductivity type being different from the first conductivity type and forming a first junction (18) to the drift layer (16), a source region (20) of the first conductivity type forming a second junction (21) to the well layer (27), and an island region (30) of the second conductivity type attaching the source region (20) such that the source region (20) separates the island region (30) from the well layer (27) in at least 50% of an island surface area of the island region (30) in the semiconductor body (11).

A silicon carbide substrate includes a first main surface and a second main surface opposite to the first main surface. A void is present in the silicon carbide substrate. An area density of the void in the first main surface is 0.7/cm.sup.2 or less. A width of the void is 10 m to 80 m when viewed in a direction perpendicular to the first main surface. In a cross-section perpendicular to the first main surface, the width of the void decreases from the first surface toward the second surface when viewed in a direction parallel to the first main surface. A depth of the void is larger than or equal to the width of the void in the first main surface and smaller than a thickness of the silicon carbide substrate when viewed in the direction parallel to the first main surface.

A method of manufacturing a superjunction silicon carbide semiconductor device is provided, enabling a reduction of the number of times a combination of epitaxial growth and ion implantation for forming a parallel pn structure is performed. In the method of manufacturing the superjunction silicon carbide semiconductor device, forming an epitaxial layer 2a, 2b of a second conductivity type on a front surface of a silicon carbide semiconductor substrate 1 of a first conductivity type and selectively forming semiconductor regions 4a, 4b of the first conductivity type by implanting nitrogen ions in the epitaxial layer are repeated multiple times, thereby forming the parallel pn structure.

A method for separating dies from a semiconductor substrate having dies adjoining a first surface of the substrate includes: attaching the substrate to a carrier via the first surface; generating first modifications by introducing laser irradiation into an interior of the substrate via a second surface of the substrate, the first modifications extending between the first surface and a vertical level in the interior that is being spaced from the second surface, the first modifications laterally surrounding the dies; generating second modifications by introducing laser irradiation into the interior via the second surface, the second modifications sub-dividing the substrate into a first part between the first surface and the second modifications, and a second part between the second surface and the second modifications; separating the parts along a first separation area defined by the second modifications; and separating the dies along a second separation area defined by the first modifications.

A semiconductor rectifier device comprises: an epitaxial layer having a top surface and a bottom surface; a first trench comprising a first side wall, a second side wall, and a first bottom surface; a second trench adjacent to the first trench, the second trench comprising a third side wall, a fourth side wall, and a second bottom surface; a first doped region abutting against the first side wall and at least a part of the first bottom surface of the first trench; a second doped region adjacent to and separated from the first doped region, wherein the second doped region abuts against the third side wall, the fourth side wall and the second bottom surface of the second trench; a gate structure disposed on the top surface between the first trench and the second trench; and a contact metal layer disposed on the top surface of the epitaxial layer.

The present disclosure relates to a power semiconductor device (100) comprising a silicon carbide semiconductor. SiC. structure (110) comprising a SiC epilayer (112), at least one ohmic contact (120) formed on a first main surface (114) of the SiC structure (110), and at least Schottky barrier contact (130) formed on a second main surface (116) of the SiC structure (110). The at least one Schottky barrier contact (130) comprises a metal layer (136) and a carbon group interlayer (134) arranged between the metal layer (136) and the second main surface (116) of the SiC structure (110). 15 The present disclosure relates to a Schottky barrier diode (400). a vertical field effect transistor, such as a power MOSFET (500), and a method for manufacturing a power semiconductor device (100).

devices and methods of forming a semiconductor device that includes a deep shielding pattern that may improve a reliability and/or a functioning of the device. An example method may include forming a wide band-gap semiconductor layer structure on a substrate, the semiconductor layer structure including a drift region that has a first conductivity type; forming a plurality of gate trenches in an upper portion of the semiconductor layer structure, the gate trenches spaced apart from each other, each gate trench having a bottom surface, a first sidewall, a second sidewall, and an upper opening; forming an obstruction over a portion of each gate trench that partially obscures the upper opening; and implanting dopants having a second conductivity type that is opposite the first conductivity type into the bottom surfaces of the gate trenches, where the dopants implanted into the bottom surface of the gate trenches form deep shielding patterns.

Shielded gate semiconductor devices are disclosed for use in high power applications such as electric vehicles and industrial applications. The devices are formed as mesa (106)/trench (400) structures in which shielded gate electrodes are formed in the trenches. Various trench structures (400, 500, 600, 700) are presented that include tapered portions (401) and end tabs (502, 602, 702, 802) that can be beneficial in managing the distribution of electric charge and associated electric fields. The tapered trenches (400) can be used to increase and stabilize breakdown voltages in a termination region (104) of a semiconductor die (100).

A molding is formed by laminating an aggregate of SiC and a paste containing Si and C powders on an epitaxial layer of SiC formed on a support substrate of SiC to form an intermediate sintered body in which polycrystalline SiC is produced from the Si and C powders by reaction sintering, free Si is carbonized to SiC to form a sintered body layer, and the support substrate is removed from the epitaxial layer to form a semiconductor substrate in which the epitaxial layer and the sintered body layer are laminated.

Disclosed examples include microelectronic devices, e.g. Integrated circuits. One example includes a microelectronic device including a nanosheet lateral drain extended metal oxide semiconductor (LDMOS) transistor with source and drain regions having a first conductivity type extending into a semiconductor substrate having an opposite second conductivity type. A superlattice of alternating layers of nanosheets of a channel region and layers of gate conductor are separated by a gate dielectric, the superlattice extending between the source region and the drain region. A drain drift region of the first conductivity type extends under the drain region and a body region of the second type extends around the source region.