A microelectronic device, e.g. an integrated circuit, includes first and second doped semiconductor regions over a semiconductor substrate. A semiconductor nanosheet layer is connected between the first and second semiconductor regions and has a bandgap greater than 1.5 eV. In some examples such a device is implemented as an LDMOS transistor. A method of forming the device includes forming a trench in a semiconductor substrate having a first conductivity type. A semiconductor nanosheet stack is formed within the trench, the stack including a semiconductor nanosheet layer and a sacrificial layer. Source and drain regions having an opposite second conductivity type are formed extending into the semiconductor nanosheet stack. The sacrificial layer between the source region and the drain region is removed, and the semiconductor nanosheet layer is annealed. A gate dielectric layer is formed on the semiconductor nanosheet layer, and a gate conductor is formed on the gate dielectric layer.

A SiC epitaxial wafer includes a SiC substrate and an epitaxial layer laminated on the SiC substrate, wherein the epitaxial layer contains an impurity element which determines the conductivity type of the epitaxial layer and boron which has a conductivity type different from the conductivity type of the impurity element, and the concentration of boron is less than 1.010.sup.14 cm.sup.3 at any position in the plane of the epitaxial layer.

A silicon carbide wafer includes a base wafer that is made of silicon carbide and doped with an n-type impurity, and an epitaxial layer that is arranged on a main surface of the base wafer, made of silicon carbide and doped with an n-type impurity. The base wafer has a thickness t1 and an average impurity concentration n1, and the epitaxial layer has a thickness t2 and an average impurity concentration n2. The base wafer and the epitaxial layer are configured so as to satisfy a mathematical formula 1:
0.0178<0.012+(t2/t1)0.057(n2/n1)0.029{(t2/t1)0.273}{(n2/n1)0.685}0.108<0.0178.[Formula 1]

A method of forming a gate structure on a substrate with increased charge mobility. In some embodiments, the method may include depositing an amorphous carbon layer on a silicon carbide layer on the substrate to form a capping layer on the silicon carbide layer, annealing the silicon carbide layer at a temperature of greater than approximately 1800 degrees Celsius, forming a hard mask on the silicon carbide layer by patterning the amorphous carbon layer, etching a trench structure of the gate structure into the silicon carbide layer using the hard mask, removing the hard mask to expose the silicon carbide layer, depositing a silicon dioxide layer on the silicon carbide layer using an ALD process, performing at least one interface treatment on the silicon dioxide layer, depositing a gate oxide layer of the gate structure on the silicon dioxide layer, and depositing a gate material on the gate oxide layer.

A semiconductor device of embodiments includes: a silicon carbide layer having a first face and a second face and including a first trench, a second trench having a distance of 100 nm or less from the first trench, a first silicon carbide region of n-type, a second silicon carbide region of p-type between the first trench and the second trench, a third silicon carbide region of n-type between the second silicon carbide region and the first face, a fourth silicon carbide region between the first trench and the second silicon carbide region and containing oxygen, and a fifth silicon carbide region between the second trench and the second silicon carbide region and containing oxygen; a first gate electrode in the first trench; a second gate electrode in the second trench; a first gate insulating layer; a second gate insulating layer; a first electrode; and a second electrode.

A power semiconductor device includes a semiconductor layer of silicon carbide (SiC), at least one trench that extends in one direction, a gate insulating layer disposed on at least an inner wall of the at least one trench, at least one gate electrode layer disposed on the gate insulating layer, a drift region disposed in the semiconductor layer at least on one side of the at least one gate electrode layer, a well region disposed in the semiconductor layer to be deeper than the at least one gate electrode layer, a source region disposed in the well region, and at least one channel region disposed in the semiconductor layer of one side of the at least one gate electrode layer between the drift region and the source region.

A power device includes a substrate, a drift layer disposed on the substrate, a terminal region and an active region disposed in the drift layer, an electrode layer disposed on the active region, a Schottky contact layer disposed between the electrode layer and the active region, a passivation layer disposed on the drift layer, and an isolation layer disposed between the passivation layer and the electrode layer so that the passivation layer and the electrode layer are at least partially separated from each other. The isolation layer, the electrode layer, and the passivation layer each respectively has a thermal expansion coefficient a, b, c, and a>b>c.

A charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) device may include a charge balanced (CB) layer defined within a first epitaxial (epi) layer that has a first conductivity type. The CB layer may include charge balanced (CB) regions that has a second conductivity type. The CB trench-MOSFET device may include a device layer defined in a second epi layer and having the first conductivity type, where the device layer is disposed on the CB layer. The device layer may include a source region, a base region, a trench feature, and a shield region having the second conductivity type disposed at a bottom surface of the trench feature. The device layer may also include a charge balanced (CB) bus region having the second conductivity type that extends between and electrically couples the CB regions of the CB layer to at least one region of the device layer having the second conductivity type.

Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.

A process of forming a gate insulating film in a silicon carbide semiconductor device. The process includes performing a first stage of a nitriding heat treatment by a gas containing oxygen and nitrogen, followed by depositing an oxide film, and then performing a second stage of the nitriding heat treatment by a gas containing nitric oxide and nitrogen. The amount of nitrogen at the treatment starting point of the first stage of the nitriding heat treatment is greater than the amount of nitrogen at the treatment starting point of the second stage of the nitriding heat treatment. The amount of nitrogen at the treatment ending point of the second stage of the nitriding heat treatment is greater than the amount of nitrogen at the treatment ending point of the first stage of the nitriding heat treatment.