A method for forming an ohmic contact on a semiconductor component, for example a high-power electrical diode, is provided. An example method includes depositing a first metal layer on a top surface of a semiconductor drift layer having an electrical contact point, the first metal layer highly reflective of a laser light. The method further includes depositing a second metal layer on portions of the first metal layer aligned with the electrical contact point, the second metal layer selected to absorb the laser light. The method further includes exposing the first and the second metal layers to the laser light in a laser annealing process, causing the second metal layer to substantially increase in temperature due to the laser light. The increase in temperature of the second metal layer causing the ohmic contact to form between the electrical contact point and the first metal layer.

The present disclosure provides a method of manufacturing a semiconductor substrate. The method includes: forming a graphene layer on a silicon plane of a silicon carbide monocrystalline substrate; forming a SiC epitaxial growth layer on the graphene layer; forming a stress layer on the SiC epitaxial growth layer; attaching a temporary substrate onto the stress layer; peeling off the graphene layer from the SiC epitaxial growth layer; forming a SiC polycrystalline growth layer on a carbon plane of the SiC epitaxial growth layer from which the graphene layer has been peeled off; and removing the temporary substrate. At least one of the forming of the graphene layer and the forming of the SiC epitaxial growth layer is under an atmosphere including fluorine.

An electronic device comprising: a semiconductor body of silicon carbide, SiC, having a first and a second face, opposite to one another along a first direction, which presents positive-charge carriers at said first face that form a positive interface charge; a first conduction terminal, which extends at the first face of the semiconductor body; a second conduction terminal, which extends on the second face of the semiconductor body; a channel region in the semiconductor body, configured to house, in use, a flow of electrons between the first conduction terminal and the second conduction terminal; and a trapping layer, of insulating material, which extends in electrical contact with the semiconductor body at said channel region and is designed so as to present electron-trapping states that generate a negative charge such as to balance, at least in part, said positive interface charge.

A semiconductor rectifier device comprises: an epitaxial layer having a top surface and a bottom surface; a first trench comprising a first side wall, a second side wall, and a first bottom surface; a second trench adjacent to the first trench, the second trench comprising a third side wall, a fourth side wall, and a second bottom surface; a first doped region abutting against the first side wall and at least a part of the first bottom surface of the first trench; a second doped region adjacent to and separated from the first doped region, wherein the second doped region abuts against the third side wall, the fourth side wall and the second bottom surface of the second trench; a gate structure disposed on the top surface between the first trench and the second trench; and a contact metal layer disposed on the top surface of the epitaxial layer.

Semiconductor device has a cell region and a peripheral region, and has a drift layer, a trench, an gate dielectric film on an inner wall of the trench, a gate electrode, and a p-type first semiconductor region below the trench in the cell region on a semiconductor substrate. Further, in the peripheral region on the semiconductor substrate, p-type second semiconductor region is formed in the same layer as the p-type first semiconductor region, a width of the p-type first semiconductor region and a width of the p-type second semiconductor region are different.

The SiC substrate has a warpage factor F of 300 m or less, which is obtained from the thickness, the diameter, and a stress at a first outer circumferential end 10 mm inward from an outer circumferential end in the [11-20] direction from a center thereof.

The present application discloses a Schottky barrier diode device and a manufacturing method therefor. The Schottky barrier diode device comprises an epitaxial wafer having an epitaxial layer. The epitaxial layer comprising a first surface and a second surface that are opposite to each other, and the first surface being provided with a functional region and trench regions located on both sides of the functional region; multi-level trenches located in the trench regions, each of the multi-level trenches comprising: multiple sub-trenches, the multiple sub-trenches successively comprising a first-level sub-trench to an Nth-level sub-trench in a first direction; the width of the sub-trenches in the same multi-level trench being sequentially increased in the first direction. The side wall of at least the first-level sub-trench being provided with a side wall protection structure.

The semiconductor device includes a chip which has a first surface on one side and a second surface on the other side, a plurality of IGBT regions which are provided at an interval in the chip, a boundary region which is provided in a region between the plurality of IGBT regions in the chip, a first conductivity type cathode region which is formed in a surface layer portion of the second surface in the boundary region, and a second conductivity type well region which is formed in a surface layer portion of the first surface in the boundary region.

A transistor device and a method for manufacturing a transistor device are disclosed. The transistor device includes a semiconductor body and a plurality of transistor cells. Each transistor cell includes: a drift region, a body region, and a source region; a gate electrode connected to a gate node; and a field electrode connected to a source node. The gate electrode is dielectrically insulated from the body region by a gate dielectric, and is arranged in a first trench extending from a first surface into the semiconductor body. The field electrode is dielectrically insulated from the drift region by a high-k dielectric, and is arranged in a second trench. The second trench extends from the first surface into the semiconductor body and is spaced apart from the first trench, and the field electrode extends at least as deep as the first trench into the semiconductor body.

A semiconductor device includes: a semiconductor substrate; an epitaxial layer or layer stack on the semiconductor substrate; a plurality of transistor cells of a first type formed in a first region of the epitaxial layer or layer stack and electrically coupled in parallel to form a vertical power transistor; a plurality of transistor cells of a second type different than the first type and formed in a second region of the epitaxial layer or layer stack; and an isolation structure that laterally and vertically delimits the second region of the epitaxial layer or layer stack. Sidewalls and a bottom of the isolation structure include a dielectric material that electrically isolates the plurality of transistor cells of the second type from the plurality of transistor cells of the first type in the epitaxial layer or layer stack. Methods of producing the semiconductor device are also described.