An object is to provide a technique that enhances the reliability of a silicon carbide semiconductor device without impairing the productivity of the silicon carbide semiconductor device. In a semiconductor structure, an active region and a terminal region connected to the active region along the outer periphery of the active region are defined, a silicon carbide substrate includes a high resistance region provided in the termination region, or provided in the termination region and a portion of the active region that is in contact with the termination region, and in contact with the buffer layer, and resistance of the high resistance region is higher than resistance of a remaining region of the silicon carbide substrate other than the high resistance region.

An SiC semiconductor device includes an SiC semiconductor layer having a first main surface and a second main surface, a gate electrode embedded in a trench with a gate insulating layer, a source region of a first conductivity type formed in a side of the trench in a surface layer portion of the first main surface, a body region of a second conductivity type formed in a region at the second main surface side with respect to the source region in the surface layer portion of the first main surface, a drift region of the first conductivity type formed in a region at the second main surface side in the SiC semiconductor layer, and a contact region of the second conductivity type having an impurity concentration of not more than 1.010.sup.20 cm.sup.3 and formed in the surface layer portion of the first main surface.

At a front surface of a silicon carbide base, an n.sup.-type drift layer, a p-type base layer, a first n.sup.+-type source region, a second n.sup.+-type source region, and a trench that penetrates the first and the second n.sup.+-type source regions and the p-type base layer and reaches the n-type region are provided. In the trench, the gate electrode is provided via a gate insulating film, an interlayer insulating film is provided in the trench on the gate electrode.

A semiconductor module includes an IGBT device, and a MISFET device that composes a parallel circuit together with the IGBT device. The semiconductor module generates a drain current of the MISFET device in a voltage range less than a built-in voltage of the IGBT device and generates a collector current of the IGBT device and a drain current of the MISFET device in a voltage range equal to or more than the built-in voltage.

A silicon carbide wafer and a method of fabricating the same are provided. In the silicon carbide wafer, a ratio (V:N) of a vanadium concentration to a nitrogen concentration is in a range of 2:1 to 10:1, and a portion of the silicon carbide wafer having a resistivity greater than 10.sup.12 .Math.cm accounts for more than 85% of an entire wafer area of the silicon carbide wafer.

There is described a semiconductor device comprising an SiC body with a gate structure comprising a gate dielectric with a specific multilayer laminate structure including alternating layers of a first dielectric material and of a second dielectric material having a dielectric constant of 4 or higher. There is further described a method for manufacturing such a semiconductor device including an SiC body as mentioned before.

A semiconductor device includes an active region, which is a region where main current flows, an edge termination region surrounding the active region, a step surface surrounding the edge termination region, and a dicing line surrounding the step surface. The active region has a first pn junction of a first semiconductor region and a second semiconductor layer and a second pn junction of an outer peripheral region and the second semiconductor layer. The step surface is provided with a first protective film for shielding light generated as forward current flows through the first and second pn junctions in the active region.

A method of recycling silicon wastewater includes forming a silicon slurry from the silicon wastewater using a micro filtration device, forming a silicone cake from the silicon slurry using a filter press, and forming a silicon powder by drying the silicone cake in a reducing atmospheric.

Disclosed is a silicon carbide power semiconductor device and, more particularly, a silicon carbide power semiconductor device capable of improving on-resistance characteristics by contacting at least one lowermost surface of a base or a source with an underlying JFET region.

A method for manufacturing a silicon carbide epitaxial substrate which has a first surface which is a (000-1) C-face, a silicon carbide epitaxial layer located on the first surface of the silicon carbide substrate, and a line-shaped surface defect density on a top surface of the silicon carbide epitaxial layer is less than 1.0 cm.sup.2 and a stacking fault density is less than 1.2 cm.sup.2.