A superlattice cell that includes Group IV elements is repeated multiple times so as to form the superlattice. Each superlattice cell has multiple ordered atomic planes that are parallel to one another. At least two of the atomic planes in the superlattice cell have different chemical compositions. One or more of the atomic planes in the superlattice cell one or more components selected from the group consisting of carbon, tin, and lead. These superlattices make a variety of applications including, but not limited to, transistors, light sensors, and light sources.

Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.

Semiconductor devices having group III-V material active regions and graded gate dielectrics and methods of fabricating such devices are described. In an example, a semiconductor device includes a group III-V material channel region disposed above a substrate. A gate stack is disposed on the group III-V material channel region. The gate stack includes a graded high-k gate dielectric layer disposed directly between the III-V material channel region and a gate electrode. The graded high-k gate dielectric layer has a lower dielectric constant proximate the III-V material channel region and has a higher dielectric constant proximate the gate electrode. Source/drain regions are disposed on either side of the gate stack.

A MISFET is formed to include: a co-doped layer that is formed over a substrate and has an n-type semiconductor region and a p-type semiconductor region; and a gate electrode formed over the co-doped layer via a gate insulation film. The co-doped layer contains a larger amount of Mg, a p-type impurity, than that of Si, an n-type impurity. Accordingly, the carriers (electrons) resulting from the n-type impurities (herein, Si) in the co-doped layer are canceled by the carriers (holes) resulting from p-type impurities (herein, Mg), thereby allowing the co-doped layer to serve as the p-type semiconductor region. Mg can be inactivated by introducing hydrogen into, of the co-doped layer, a region where the n-type semiconductor region is to be formed, thereby allowing the region to serve as the n-type semiconductor region. By thus introducing hydrogen into the co-doped layer, the p-type semiconductor region and the n-type semiconductor region can be formed in the same layer.

Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.

An electronic device includes a trigonal crystal substrate defining a (0001) C-plane. The substrate may comprise Sapphire or other suitable material. A plurality of rhombohedrally aligned SiGe (111)-oriented crystals are disposed on the (0001) C-plane of the crystal substrate. A first region of material is disposed on the rhombohedrally aligned SiGe layer. The first region comprises an intrinsic or doped Si, Ge, or SiGe layer. The first region can be layered between two secondary regions comprising n+doped SiGe or n+doped Ge, whereby the first region collects electrons from the two secondary regions.

A bipolar junction transistor includes an intrinsic base formed on a substrate. The intrinsic base includes a superlattice stack including a plurality of alternating layers of semiconductor material. A collector and emitter are formed adjacent to the intrinsic base on opposite sides of the base. An extrinsic base structure is formed on the intrinsic base.

An aspect of the disclosure includes a semiconductor structure comprising: a set of fins on a substrate, the set of fins including a relaxed silicon germanium layer; and a dielectric between each fin in the set of fins; wherein each fin in a n-type field effect transistor (nFET) region further includes a strained silicon layer over the relaxed silicon germanium layer of each fin in the nFET region; wherein each fin in a p-type field effect transistor (pFET) region further includes a strained silicon germanium layer over the relaxed silicon germanium layer of each fin in the pFET region.

A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer, a third nitride semiconductor layer formed over the second nitride semiconductor layer, a fourth nitride semiconductor layer formed over the third nitride semiconductor layer, a trench that penetrates the fourth nitride semiconductor layer and reaches as far as the third nitride semiconductor layer, a gate electrode disposed by way of a gate insulation film in the trench, a first electrode and a second electrode formed respectively over the fourth nitride semiconductor layer on both sides of the gate electrode, and a coupling portion for coupling the first electrode and the first nitride semiconductor layer.

The present invention relates to vertical integrated, quantized FET with sharp drain and BJT with sharp emitter implemented in one nano-BiCMOS process, using multiple identical single crystalline semiconductor pyramids, placed in-situ directly on the surface of diffusion regions. The devices' gate and base structures are formed at a level of 35-45 nm below the top of the pyramids. The bottom region of the pyramids contains the collector/source structures, while the top region of the pyramids contains the emitter/drain structures. The base structure for BJT is formed by selective epitaxial growth of SiSi.sub.xGe.sub.1-xSi with opposite conductivity type as COR, and interconnected by a horizontal polysilicon grid. The self-aligned gate structure for FET is formed by high dopant implantation of impurity with the same type of conductivity as COR through horizontal gate bridge, which represent a grid of horizontal stacked layers Si.sub.3N.sub.4 high-k insulatorpolysiliconhigh-k insulatorSi.sub.3N.sub.4.