In some embodiments, the techniques described herein relate to an epitaxial oxide transistor. The transistor can include: a substrate; a channel layer including a first epitaxial semiconductor layer on the substrate; a gate layer including a second epitaxial semiconductor layer on the first epitaxial semiconductor layer; a source electrode and a drain electrode coupled to the channel layer; and a gate electrode coupled to the gate layer. The first epitaxial semiconductor layer can include a first polar oxide material and the second epitaxial semiconductor layer can include a second polar oxide material. The first polar oxide material and the second polar oxide material can include cation-polar surfaces oriented towards or away from the substrate, and the second polar oxide material can include a wider bandgap than the first polar oxide material.

To provide a resonant tunneling diode and a terahertz oscillator capable of further performance improvement. The resonant tunneling diode includes: a multi-quantum well structure that is composed of a group-III nitride semiconductor; a first electrode that is connected to one of sides of the multi-quantum well structure; and a second electrode that is connected to the other side of the multi-quantum well structure. The multi-quantum well structure includes a first barrier layer, a first quantum well layer, a second barrier layer, a second quantum well layer, and a third barrier layer, which are arranged in order from the first electrode toward the second electrode. The first barrier layer, the second barrier layer, and the third barrier layer have a thickness through which a carrier can pass by a tunneling effect. The first quantum well layer and the second quantum well layer each have a potential gradient by spontaneous polarization or a sum of spontaneous polarization and piezoelectric polarization, and have mutually different thicknesses. The first quantum well layer and the second quantum well layer have compositions with different magnitudes of potential energy.

Quantum dot devices and related methods and systems that use semiconductor nanoribbons arranged in a grid where a plurality of first nanoribbons, substantially parallel to one another, intersect a plurality of second nanoribbons, also substantially parallel to one another but at an angle with respect to the first nanoribbons, are disclosed. Different gates at least partially wrap around individual portions of the first and second nanoribbons, and at least some of the gates are provided at intersections of the first and second nanoribbons. Unlike previous approaches to quantum dot formation and manipulation, nanoribbon-based quantum dot devices provide strong spatial localization of the quantum dots, good scalability in the number of quantum dots included in the device, and/or design flexibility in making electrical connections to the quantum dot devices to integrate the quantum dot devices in larger computing devices.

A semiconductor device includes a substrate, a first active structure, a conductive portion and a first helmet. The first active structure is formed on the substrate and includes a plurality of first active channel sheets and a plurality of first metal gate structures vertically stacked to each other, wherein the topmost first metal gate structure includes a first inner spacer. The conductive portion is connected with the topmost first active channel sheet. The first helmet is formed above the first inner spacer and covers a lateral surface of the conductive portion.

A method of manufacturing a High-Electron-Mobility Transistor (HEMT) includes: preparing a substrate; forming a first buffer over the substrate; forming a second buffer over the first buffer, wherein forming the second buffer includes doping a first thickness of a material such as gallium nitride (GaN) with a first concentration of a dopant such as carbon, and doping a second thickness of the material with a second concentration of the dopant such that the second concentration of dopant has a gradient though the second thickness which progressively decreases in a direction away from the first thickness; forming a channel layer such as a GaN channel over the second buffer; forming a barrier layer such as aluminum gallium nitride (AlGaN) over the channel layer; and forming drain, source and gate terminals for the HEMT.

Silicon germanium (SiGe)/silicon containing superlattice structures and methods for forming the same are provided. Various embodiments utilize SiGe layers in a SiGe/Si superlattice structure, which include varying concentrations of germanium throughout the layer. For example, in some embodiments, for each SiGe layer there is a core SiGe film with a low Ge content and two thinner SiGe layers or cladding layers positioned on opposing sides of the core SiGe film with each of the SiGe cladding layers having a higher Ge content then the core SiGe film. Various embodiments provide for SiGe layers having a germanium depth profile enabling strained SiGe superlattice deposition on Si{110} substrates.

A semiconductor device may include a semiconductor substrate and a superlattice layer on the semiconductor substrate. The superlattice layer may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a Group III-N semiconductor stack including a plurality of layers of Group III-N semiconductor layers above the superlattice layer.

A semiconductor device may include a semiconductor substrate and a superlattice layer on the semiconductor substrate. The superlattice layer may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may also include a piezoelectric layer on the superlattice layer and comprising a Group III-N semiconductor.

A method for making a semiconductor device may include forming a semiconductor substrate, and forming a superlattice layer on the semiconductor substrate and including a plurality of stacked groups of layers. Each group of layers may including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming a Group III-N semiconductor stack comprising a plurality of layers of Group III-N semiconductor layers above the superlattice layer.

A semiconductor device may include a semiconductor substrate and a first superlattice layer on the semiconductor substrate. The first superlattice layer may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a first device layer on the first superlattice layer and comprising silicon, a second device layer on the first superlattice layer laterally adjacent the first device layer, with the second device layer comprising a Group III-N semiconductor, a first device on the first device layer, and a second device on the second device layer.