The techniques described herein relate to a transistor including a single crystal substrate, an epitaxial channel layer (ECL) on the single crystal substrate, a gate layer on the ECL, a source electrical contact coupled to the ECL, a drain electrical contact coupled to the ECL, and a gate electrical contact coupled to the gate layer. The substrate includes a substrate material with a first crystal symmetry and the ECL includes an ECL oxide material with a second crystal symmetry, where the first crystal symmetry is different from the second crystal symmetry. The gate layer includes a gate oxide material, where the ECL oxide material has a first bandgap and the gate oxide material has a second bandgap, and the second bandgap is wider than the first bandgap.

Structures that include an isotopically-depleted semiconductor layer and methods of forming such structures. The structure comprises a semiconductor layer comprising a semiconductor material having an isotope with a concentration that is less than a natural abundance of the first isotope and greater than zero parts per million.

A semiconductor device includes a first substrate having a first frontside and a first backside opposite the first frontside. The semiconductor device includes first source/drain (S/D) features over the first frontside. The semiconductor device includes a first barrier gate and a first plunger gate between the first S/D features, where the first plunger gate defines a first quantum bit region. The semiconductor device includes a second substrate having a second frontside and a second backside opposite the second frontside. The semiconductor device includes second S/D features over the second frontside. The semiconductor device includes a second barrier gate and a second plunger gate between the second S/D features, where the second plunger gate defines a second quantum bit region aligned with the first quantum bit region along the first direction. The semiconductor device includes a doped well extending between the first backside and the second backside along the first direction.

A semiconductor structure is provided. The semiconductor structure includes a substrate, a first superlattice structure and a second superlattice structure over the substrate, a gate stack that surrounds a channel region of each of the first superlattice structures and the second superlattice structure, and source/drain structures on opposite sides of the gate stack contacting sidewalls of the first superlattice structure and the second superlattice structure. The second superlattice structure is disposed over the first superlattice structure. Each of the first superlattice structures and the second superlattice structure includes vertically stacked alternating first nanosheets of a first semiconductor material and second nanosheets of a second semiconductor material that is different from the first semiconductor material.

A method of manufacturing a High-Electron-Mobility Transistor (HEMT) includes: preparing a substrate; forming a first buffer over the substrate; forming a second buffer over the first buffer, wherein forming the second buffer includes doping a first thickness of a material such as gallium nitride (GaN) with a first concentration of a dopant such as carbon, and doping a second thickness of the material with a second concentration of the dopant such that the second concentration of dopant has a gradient though the second thickness which progressively decreases in a direction away from the first thickness; forming a channel layer such as a GaN channel over the second buffer; forming a barrier layer such as aluminum gallium nitride (AlGaN) over the channel layer; and forming drain, source and gate terminals for the HEMT.

Disclosed is a semiconductor structure including a device (e.g., a bi-directional semiconductor-controlled rectifier, such as a bi-directional silicon-controlled rectifier (BDSCR)) and, within the device, at least two dual-level isolation structures. Each dual-level isolation structure includes a first section at the top surface of the semiconductor substrate and one or more second sections extending through the first section deeper into the semiconductor substrate. The dual-level isolation structures are positioned within the device so as to increase well resistance. By increasing well resistance, the trigger voltage of the device can be reduced without increasing device size. Also disclosed is a method of forming dual-level isolation structures within such a device.

Disclosed is a semiconductor structure including a device (e.g., a bi-directional semiconductor-controlled rectifier, such as a bi-directional silicon-controlled rectifier (BDSCR)) and, within the device, at least two dual-level isolation structures. Each dual-level isolation structure includes a first section at the top surface of the semiconductor substrate and one or more second sections extending through the first section deeper into the semiconductor substrate. The dual-level isolation structures are positioned within the device so as to increase well resistance. By increasing well resistance, the trigger voltage of the device can be reduced without increasing device size. Also disclosed is a method of forming dual-level isolation structures within such a device.

A radio frequency (RF) semiconductor device may include a semiconductor-on-insulator substrate, and an RF ground plane layer on the semiconductor-on-insulator substrate including a conductive superlattice. The conductive superlattice may include stacked groups of layers, with each group of layers comprising stacked doped base semiconductor monolayers defining a doped base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent doped base semiconductor portions. The RF semiconductor device may further include a body above the RF ground plane layer, spaced apart source and drain regions adjacent the body and defining a channel region in the body, and a gate overlying the channel region.

Various embodiments of the present disclosure are directed towards an integrated chip a semiconductor device including a plurality of superlattice layers disposed over a substrate. The plurality of superlattice layers include a first superlattice layer overlying a second superlattice layer. A channel layer overlies the plurality of superlattice layers. An active layer overlies the channel layer. A first interlayer buffer layer is disposed directly between the first superlattice layer and the second superlattice layer. The first interlayer buffer layer comprises a first density of dislocations greater than a second density of dislocations in the first superlattice layer.

A bipolar junction transistor (BJT) may include a substrate defining a collector region therein. A first superlattice may be on the substrate including a plurality of stacked groups of first layers, with each group of first layers including a first plurality of stacked base semiconductor monolayers defining a first base semiconductor portion, and at least one first non-semiconductor monolayer constrained within a crystal lattice of adjacent first base semiconductor portions. Furthermore, a base may be on the first superlattice, and a second superlattice may be on the base including a second plurality of stacked groups of second layers, with each group of second layers including a plurality of stacked base semiconductor monolayers defining a second base semiconductor portion, and at least one second non-semiconductor monolayer constrained within a crystal lattice of adjacent second base semiconductor portions. An emitter may be on the second superlattice.