A semiconductor gate-all-around (GAA) device may include a semiconductor substrate, source and drain regions on the semiconductor substrate, a plurality of semiconductor nanostructures extending between the source and drain regions, a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement, and a dopant diffusion liner adjacent at least one of the source and drain regions and comprising a first superlattice. The first superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

A semiconductor gate-all-around (GAA) device may include a semiconductor substrate, source and drain regions on the semiconductor substrate, a plurality of semiconductor nanostructures extending between the source and drain regions, a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement, and a dopant diffusion liner adjacent at least one of the source and drain regions and comprising a first superlattice. The first superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

The techniques described herein relate to a transistor, including a substrate, an epitaxial buffer layer, an epitaxial channel layer, and a gate layer. The substrate includes a first oxide material with a first crystal symmetry, the epitaxial buffer layer includes a second oxide material with a second crystal symmetry, the epitaxial channel layer includes a third oxide material with a third crystal symmetry and a first bandgap, and the gate layer includes a fourth oxide material with a second bandgap. The first crystal symmetry is different from either the second crystal symmetry or the third crystal symmetry, and the second bandgap is wider than the first bandgap. The transistor also includes electrical contacts including a source electrical contact coupled to the epitaxial channel layer, a drain electrical contact coupled to the epitaxial channel layer, and a gate electrical contact coupled to the gate layer.

A method is provided for operating a fractional quantum Hall apparatus including a set of interferometers, each having a cell and a set of gate electrodes located around the cell. The method includes calibrating each one of the interferometers to confine a droplet of a 2D charge carrier gas in a fractional quantum Hall effect state of filling factor 17/5 or 12/5, while a reentrant phase of integer quantum Hall effect states of the 2D charge carrier gas is located between the area of the droplet in a fractional quantum Hall effect state and the interferometer electrodes. The calibrating includes setting a value of a magnetic field across the apparatus such that the reentrant phase and the droplet of the 2D charge carrier gas are present in at least one of the interferometers based on interference measurements on at least one of the interferometers for different values of the magnetic field.

Provided are a nitride semiconductor buffer structure and a semiconductor device including the same. The buffer structure may include a plurality of buffer layers between a substrate and an active layer. The active layer may include a nitride semiconductor. The plurality of buffer layers may be stacked on each other on the substrate. Each of the plurality of buffer layers may have a super lattice structure and may include a doped nitride semiconductor. The plurality of buffer layers may have different compositions from each other. Adjacent buffer layers, among the plurality of buffer layers, may have different doping concentrations from each other.

The techniques described herein relate to a transistor including a substrate including sapphire, an epitaxial channel layer on the substrate, and an epitaxial gate layer on the channel layer. The epitaxial channel layer can include -Ga.sub.2O.sub.3, with a first bandgap. The epitaxial gate layer can include an oxide material with a second bandgap, wherein the second bandgap is wider than the first bandgap. The transistor can also include electrical contacts, including: a source electrical contact coupled to the epitaxial channel layer; a drain electrical contact coupled to the epitaxial channel layer; and a gate electrical contact coupled to the epitaxial gate layer.

A method for making a double-diffused MOS (DMOS) device may include forming a semiconductor layer having a first conductivity type, forming a drift region of a second conductivity type in the semiconductor substrate, forming spaced-apart source and drain regions in the semiconductor layer, and forming a first superlattice on the semiconductor layer. The first superlattice may include a plurality of stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming a gate above the first superlattice, and a forming field plate layer adjacent the drift region and configured to deplete the drift region.

A method for making a double-diffused MOS (DMOS) device may include forming a semiconductor layer having a first conductivity type, forming a drift region of a second conductivity type in the semiconductor substrate, forming spaced-apart source and drain regions in the semiconductor layer, and forming a first superlattice on the semiconductor layer. The first superlattice may include a plurality of stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming a gate above the first superlattice, and a forming field plate layer adjacent the drift region and configured to deplete the drift region.

A device includes a substrate and a heterostructure supported by the substrate. The heterostructure includes a III-nitride layer and a ferroelectric layer supported by the III-nitride layer. The ferroelectric layer includes a quaternary III-nitride alloy. The quaternary III-nitride alloy includes a Group IIIB element. The ferroelectric layer has a lattice constant greater than a lattice constant of gallium nitride (GaN).

The present disclosure provides a semiconductor device and a fabricating method thereof, the semiconductor device including a substrate, a nucleation layer, a buffer layer, an active layer and a gate electrode. The nucleation layer is disposed on the substrate, and the buffer layer is disposed on the nucleation layer, wherein the buffer layer includes a first superlattice layer having at least two heteromaterials alternately arranged in a horizontal direction, and a second superlattice layer having at least two heteromaterials vertically stacked along a vertical direction. The at least two heteromaterials stack at least once within the second superlattice layer. The active layer is disposed on the buffer layer, and the gate electrode is disposed on the active layer.