A CMOS imaging sensor structure and a manufacturing method therefor. The CMOS imaging sensor structure comprises a pixel unit of the CMOS imaging sensor set on a semiconductor substrate, the pixel unit comprises a circuit device region and a first photosensitive region, the circuit device region is set on the frontside of the semiconductor substrate, the first photosensitive region is set correspondingly in the semiconductor substrate below the circuit device region, the circuit device region is isolated from the first photosensitive region by an isolation region, and the circuit device region is electrical connected with the first photosensitive region through a conductive trench, a fill factor of a photosensitive region is increased, and performances of a reading circuit is increased by a more optimized design scheme. A second photosensitive region of the pixel unit can also be set on the semiconductor substrate on a side of the circuit device region, thus a larger photosensitive region can be formed together with the first photosensitive region. The present invention also provides a manufacturing method for the CMOS imaging sensor structure.

An image sensor includes a substrate having a plurality of pixel regions and a deep device isolation pattern disposed in the substrate between the pixel regions. The pixel regions include first, second, third, and fourth pixel regions, which are adjacent to each other in first and second directions. The deep device isolation pattern includes first portions interposed between the first and second pixel regions and between the third and fourth pixel regions and spaced apart from each other in the second direction, and second portions interposed between the first and third pixel regions and between the second and fourth pixel regions and spaced apart from each other in the first direction. The first pixel region includes a first extended active pattern, which is extended to the second pixel region in the first direction and is disposed between the first portions of the deep device isolation pattern.

Provided is a solid-state image capturing apparatus that can, between an image height center and positions where the image height becomes higher, align the impact of incident light with respect to light-blocking films. The solid-state image capturing apparatus is provided with a semiconductor substrate in which multiple pixels are disposed in a matrix. Each of the multiple pixels is provided with a photoelectric conversion unit that generates charge according to photoelectric conversion based on light incident on a light-receiving surface of the semiconductor substrate, a charge accumulating unit that accumulates the charge generated by the photoelectric conversion unit, a transfer transistor that transfers charge from the photoelectric conversion unit to the charge accumulating unit and has a vertical gate electrode that reaches the photoelectric conversion unit, and a light-blocking section that is formed by a trench disposed within a layer between the light-receiving surface and the charge accumulating unit and blocks light that is incident via the light-receiving surface from being incident on the charge accumulating unit. An amount of cover by the light-blocking section with respect to the charge accumulating unit is corrected according to an image height of a position where the pixel is disposed.

An imaging device according to an embodiment of the present disclosure includes: a semiconductor substrate having a first surface and a second surface opposed to each other, the semiconductor substrate including a plurality of pixels disposed in a matrix, and a plurality of photoelectric converters that each generates, through photoelectric conversion, electric charge corresponding to an amount of received light for each of the pixels; a plurality of color filters provided on a side of the first surface in respective ones of the plurality of pixels; a plurality of condensing lenses provided on a light incident side of the plurality of color filters in the respective ones of the plurality of pixels; and a separation wall provided between the plurality of color filters adjacent to each other on the side of the first surface, the separation wall having a line width on the light incident side narrower than the line width of the separation wall on the side of the first surface.

In order to solve the foregoing problem, the present disclosure provides an imaging device composed of a plurality of pixels, wherein a first pixel among the plurality of pixels includes: a first photoelectric conversion element; a first power storage unit; a first transfer element that enables a conductive state or a non-conductive state between the first photoelectric conversion element and the first power storage unit; and a first amplifying element that amplifies an image signal on the basis of a charge stored by photoelectric conversion in at least any of adjacent pixels, including a second pixel, that are adjacent to the first pixel, the second pixel including: a second amplifying element that amplifies an image signal based on a charge stored in the first power storage unit by photoelectric conversion of the first photoelectric conversion element, and a second distance between the first power storage unit and the second amplifying element is shorter than a first distance between the first power storage unit and the first amplifying element.

A solid-state image sensor is provided. The solid-state image sensor includes photoelectric conversion units and modulation structures embedded in the photoelectric conversion units. The solid-state image sensor also includes isolation structures disposed between the photoelectric conversion units and a protective layer disposed on the photoelectric conversion units. From the top view of the solid-state image sensor, the photoelectric conversion units and the modulation structures form mosaic patterns, and the ratio of the area of one modulation structure to the area of the corresponding mosaic pattern is between 0.1 and 0.9.

An apparatus includes pixels on a substrate. Each pixel includes a first portion, a second, and a microlens. The substrate has a first surface on an incidence side and a second surface opposite to the first surface, and includes an inter-pixel portion isolating adjacent pixels from each other, and an intra-pixel portion isolating the first and second portions from each other. The inter-pixel portion includes a first region located adjacently to the first surface, and a second region located adjacently to the second surface. The intra-pixel portion includes a third region located adjacently to the first surface, and a fourth region located adjacently to the second surface. The first and third regions are shifted with respect to the second and fourth regions, respectively, in an identical direction that is a direction orthogonal to a longitudinal direction of the intra-pixel portion in plan view from the first surface.

The present disclosure relates to a CMOS image sensor, and an associated method of formation. In some embodiments, the CMOS image sensor comprises a substrate and a transfer gate disposed from a front-side surface of the substrate. The CMOS image sensor further comprises a photo detecting column disposed at one side of the transfer gate within the substrate. The photo detecting column comprises a doped sensing layer comprising one or more recessed portions along a circumference of the doped sensing layer in parallel to the front-side surface of the substrate. By forming the photo detecting column with recessed portions, a junction interface is enlarged compared to a previous p-n junction interface without recessed portions, and thus a full well capacity of the photodiode structure is improved.

An image sensor includes a first photodiode group, a second photodiode group, a first transfer transistor group, a second transfer transistor group, a floating diffusion region of a substrate in which electric charges generated in the first photodiode group are stored, and a power supply node for applying a power supply voltage to the second photodiode group. A barrier voltage is applied to at least one transfer transistor of the second transfer transistor group. The power supply voltage allows electric charges, generated in the second photodiode group, to migrate to the power supply node, and the barrier voltage forms a potential barrier between the second photodiode group and the floating diffusion region.

A semiconductor device includes a pixel array comprising a first pixel and a second pixel. The semiconductor device includes a metal structure overlying a portion of a substrate between the first pixel and the second pixel. The semiconductor device includes a first barrier layer adjacent a sidewall of the metal structure. The semiconductor device includes a passivation layer adjacent a sidewall of the first barrier layer. The first barrier layer is between the passivation layer and the metal structure.