A transistor includes a gate structure with reduced gate region or eliminated gate region located between a top MDI region and a bottom MDI region. The reduced gate region has a reduction of conductive material therewithin and may be formed due to the presence of prefabricated wide inner spacers between the top MDI region and the bottom MDI region. The no gate region has an absence of conductive material therewithin and may be formed due to the presence of a prefabricated inner spacer that is between, and has a coplanar perimeter with, the top MDI region and the bottom MDI region. By reducing or eliminating the conductive material of the gate structure between the dual MDI structure, parasitic capacitance otherwise associated therewith is reduced.

A method includes forming a first semiconductor channel region and a second semiconductor channel region, with the second semiconductor channel region overlapping the first semiconductor channel region, forming a first gate dielectric on the first semiconductor channel region, and forming a second gate dielectric on the second semiconductor channel region. A dipole dopant is incorporated into a first one of the first gate dielectric and the second gate dielectric to a higher atomic percentage, and a second one of the first gate dielectric and the second gate dielectric has a lower atomic percentage of the dipole dopant. A gate electrode is formed on both of the first gate dielectric and the second gate dielectric. The gate electrode and the first gate dielectric form parts of a first transistor, and the gate electrode and the second gate dielectric form parts of a second transistor.

A semiconductor device includes a fin-type active region that extends in length in a first horizontal direction on a substrate, a horizontal semiconductor layer on the fin-type active region, a seed layer on the fin-type active region and in contact with the horizontal semiconductor layer, a gate line that surrounds the horizontal semiconductor layer and the seed layer, on the fin-type active region, and that extends in length in a second horizontal direction that intersects the first horizontal direction, and a pair of vertical semiconductor layers respectively on first and second sides of the horizontal semiconductor layer in the first horizontal direction, on the fin-type active region, with the horizontal semiconductor layer therebetween, wherein an inner wall of each of the first and second vertical semiconductor layers contacts the horizontal semiconductor layer, and upper or lower surfaces of the vertical semiconductor layers contact the seed layer.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.

An integrated circuit includes a substrate, at least one n-type semiconductor device, and at least one p-type semiconductor device. The n-type semiconductor device is present on the substrate. The n-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the n-type semiconductor device and the sidewall of the gate structure of the n-type semiconductor device intersect to form an interior angle. The p-type semiconductor device is present on the substrate. The p-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the p-type semiconductor device and the sidewall of the gate structure of the p-type semiconductor device intersect to form an interior angle smaller than the interior angle of the gate structure of the n-type semiconductor device.

A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.

In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.

Provided is a semiconductor device including a first semiconductor transistor including a semiconductor channel layer, and a metal-oxide semiconductor channel layer, and having a structure in which a second semiconductor transistor is stacked on the top of the first semiconductor transistor. A gate stack of the second semiconductor transistor and the top of a gate stack of the first semiconductor transistor may overlap by greater than or equal to 90%. The first semiconductor transistor and the second semiconductor transistor may have a similar level of operation characteristics.

A semiconductor device includes a first gate structure that includes a first interfacial layer, a first gate dielectric layer disposed over the first interfacial layer, and a first gate electrode disposed over the first gate dielectric layer. The semiconductor device also includes a second gate structure that includes a second interfacial layer, a second gate dielectric layer disposed over the second interfacial layer, and a second gate electrode disposed over the second gate dielectric layer. The first interfacial layer contains a different amount of a dipole material than the second interfacial layer.