A thin film transistor, an array substrate and a display device are provided. The thin film transistor is on a base substrate and includes a gate electrode, a first electrode, and a second electrode on the base substrate. The gate electrode includes a first body portion and a first extension portion extending along the first direction, electrically connected with the first body portion, and spaced apart from the first body portion by a first spacing. The first electrode includes a first overlapping end, an orthographic projection of the first overlapping end on the base substrate at least partially overlaps with an orthographic projection of the first body portion on the base substrate; a first compensation end at a side of the first overlapping end away from the first body portion, an orthographic projection of the first compensation end on the base substrate at least partially overlaps with an orthographic projection of the first extension portion on the base substrate; and a first intermediate portion connecting the first overlapping end and the first compensation end, an orthographic projection of the first intermediate portion on the base substrate is within an orthographic projection of the first spacing on the base substrate.

Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is off (Vg approximately 0 volts). When the transistor is on (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. Space efficient Body tie constructions adapted for cascode configurations are also described.

Various embodiments of the present disclosure provide a method for forming a recessed gate electrode that has high thickness uniformity. A gate dielectric layer is deposited lining a recess, and a multilayer film is deposited lining the recess over the gate dielectric layer. The multilayer film comprises a gate electrode layer, a first sacrificial layer over the gate dielectric layer, and a second sacrificial layer over the first sacrificial dielectric layer. A planarization is performed into the second sacrificial layer and stops on the first sacrificial layer. A first etch is performed into the first and second sacrificial layers to remove the first sacrificial layer at sides of the recess. A second etch is performed into the gate electrode layer using the first sacrificial layer as a mask to form the recessed gate electrode. A third etch is performed to remove the first sacrificial layer after the second etch.

A super-steep switching device is provided. The super-steep switching device may include a substrate, a semiconductor channel on the substrate, a source electrode and a drain electrode, which are disposed on the semiconductor channel and spaced apart from each other, a gate electrode overlapping a portion of the semiconductor channel and not overlapping a remaining portion of the semiconductor channel, and an insulating layer disposed between the gate electrode and the semiconductor channel and covering an entire surface of the semiconductor channel.

The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device includes: a substrate; an insulating layer provided with a plurality of trenches extending in a first direction; a first electrode layer and a second electrode layer, where a spacing region is provided between the first electrode layer and the second electrode layer; a semiconductor layer covering bottom portions and sidewalls of all channel trenches, where the channel trenches are at least a part of trench bodies of the trenches located in the spacing region; a gate dielectric layer covering a surface of the semiconductor layer in the channel trenches on a side away from the bottom portions and the sidewalls of the channel trenches; a gate layer, where at least a part of the channel trenches are fully filled with the gate layer.

A self-aligned transistor including an oxide semiconductor film, which has excellent and stable electrical characteristics, is provided. A semiconductor device is provided with a transistor that includes an oxide semiconductor film, a gate electrode overlapping with part of the oxide semiconductor film, and a gate insulating film between the oxide semiconductor film and the gate electrode. The oxide semiconductor film includes a first region and second regions between which the first region is positioned. The second regions include an impurity element. A side of the gate insulating film has a depressed region. Part of the gate electrode overlaps with parts of the second regions in the oxide semiconductor film.

The present invention provides a manufacture method of a TFT substrate structure and a TFT substrate structure. In the manufacture method of the TFT substrate structure, as manufacturing the gate, a plurality of metal sections distributed in spaces are formed at two sides of the gate, and the gate and the plurality of metal sections are employed to be a mask to implement ion implantation to the polysilicon layer. In the TFT substrate structure according to the present invention, the undoped areas are formed among the n-type heavy doping areas while forming the n-type heavy doping areas at the polysilicon layer.

A thin film transistor can include a substrate, a gate electrode on the substrate, a first electrode located on the substrate and surrounded by the gate electrode, a second electrode located on the first electrode and surrounded by the gate electrode, and a channel layer located between the first electrode and the second electrode. The gate electrode can include a first margin metal layer on the substrate and a second metal layer located on the first margin metal layer. A method for manufacturing the thin film transistor is also provided.

Provided is an oxide semiconductor thin film transistor with low parasitic capacitance and high reliability. A thin film transistor includes a substrate, an oxide semiconductor layer including a channel region, a source region, and a drain region, a gate insulating film, and a gate electrode. The gate insulating film includes one layer or two layers, at least one of the layers of the gate insulating film is a patterned gate insulating film located at a position separated from the source electrode and the drain electrode. A length of a lower surface of the patterned gate insulating film in a channel length direction is greater than a length of a lower surface of the gate electrode in the channel length direction. The length of the lower surface of the patterned gate insulating film in the channel length direction is greater than a length of the channel region in the channel length direction. The source region and the drain region have a higher hydrogen concentration than the channel region.

In one example, a method for fabricating a semiconductor device includes forming a mandrel comprising silicon. Sidewalls of the silicon are orientated normal to the <111> direction of the silicon. A nanowire is grown directly on at least one of the sidewalls of the silicon and is formed from a material selected from Groups III-V. Only one end of the nanowire directly contacts the silicon.