A semiconductor device includes a first insulating layer having a first side wall, an oxide semiconductor layer located on the first side wall, a gate insulating layer located on the oxide semiconductor layer, the oxide semiconductor layer being located between the first side wall and the gate insulating layer, a gate electrode facing the oxide semiconductor layer located on the first side wall, the gate insulating layer being located between the oxide semiconductor layer and the gate electrode, a first electrode located below the oxide semiconductor layer and connected with one portion of the oxide semiconductor layer, and a second electrode located above the oxide semiconductor layer and connected with the other portion of the oxide semiconductor layer.

A semiconductor device which includes a transistor having a miniaturized structure is provided. A first insulator is provided over a stack in which a semiconductor, a first conductor, and a second conductor are stacked in this order. Over the first insulator, an etching mask is formed. Using the etching mask, the first insulator and the second conductor are etched until the first conductor is exposed. After etching the first conductor until the semiconductor is exposed so as to form a groove having a smaller width than the second conductor, a second insulator and a third conductor are formed sequentially.

A transistor in which a change in characteristics is small is provided. A circuit, a semiconductor device, a display device, or an electronic device in which a change in characteristics of the transistor is small is provided. The transistor includes an oxide semiconductor; a channel region is formed in the oxide semiconductor; the channel region contains indium, an element M, and zinc; the element M is one or more selected from aluminum, gallium, yttrium, tin, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium; a gate insulator contains silicon and oxygen whose atomic number is 1.5 times or more as large as the atomic number of silicon; the carrier density of the channel region is higher than or equal to 110.sup.9 cm.sup.3 and lower than or equal to 510.sup.16 cm.sup.3; and the energy gap of the channel region is higher than or equal to 2.7 eV and lower than or equal to 3.1 eV.

Provided are electronic devices and methods of manufacturing same. An electronic device includes an energy barrier forming layer on a substrate, an upper channel material layer on the substrate, and a gate electrode that covers the upper channel material layer and the energy barrier forming layer. The gate electrode includes a side gate electrode portion that faces a side surface of the energy barrier forming layer. The side gate electrode may be configured to cause an electric field to be applied directly on the energy barrier forming layer via the side surface of the energy barrier forming layer, thereby enabling adjustment of the energy barrier between the energy barrier forming layer and the upper channel material layer. The electronic device may further include a lower channel material layer that is provided on the substrate and does not contact the upper channel material layer.

An array substrate, a manufacturing method thereof, a display device, a thin-film transistor (TFT) and a manufacturing method thereof are disclosed. The method for manufacturing the TFT comprises: forming a pattern of an active layer and a gate insulating layer provided with a metal film on a base substrate; patterning the metal film by one patterning process, and forming patterns of a gate electrode, a source electrode, a drain electrode, a gate line and a data line; forming a passivation layer on the base substrate; patterning the passivation layer by one patterning process, and forming a source contact hole, a drain contact hole and a bridge structure contact hole; and forming a transparent conductive film on the base substrate, and removing partial transparent conductive film to form a source contact portion, a drain contact portion (214), a pixel electrode and a bridge structure. The manufacturing method can reduce the number of the patterning processes.

A semiconductor device includes an oxide semiconductor layer, a gate electrode facing the oxide semiconductor layer, a gate insulating layer between the oxide semiconductor layer and the gate electrode, a first barrier layer below the oxide semiconductor layer, and a second barrier layer above the oxide semiconductor layer, the second barrier layer covering a top surface and side surfaces of the oxide semiconductor layer and being in contact with the first barrier layer in a region around the oxide semiconductor layer.

Oxide layers which contain at least one metal element that is the same as that contained in an oxide semiconductor layer including a channel are formed in contact with the top surface and the bottom surface of the oxide semiconductor layer, whereby an interface state is not likely to be generated at each of an upper interface and a lower interface of the oxide semiconductor layer. Further, it is preferable that an oxide layer, which is formed using a material and a method similar to those of the oxide layers be formed over the oxide layers Accordingly, the interface state hardly influences the movement of electrons.

An array substrate and a display device are disclosed. The array substrate includes a peripheral area in which a plurality of gate electrode material lines, a plurality of source-drain electrode material lines and a plurality of first metal lines are disposed. Overlapping areas are provided between or among the gate electrode material lines, the source-drain material lines and the first metal lines; a number of the overlapping areas of the source-drain material lines and the first metal lines is less than a number of the overlapping areas of the source-drain material lines and the gate electrode material lines; the gate electrode material lines, the source-drain material lines and the first metal lines are configured as connecting lines of circuits in the peripheral area.

An apparatus and method, the apparatus comprising: at least one charged substrate (3); a channel of two dimensional material (5); and at least one floating electrode (7A-C) wherein the floating electrode comprises a first area (10A-C) adjacent the at least one charged substrate, a second area (11A-C) adjacent the channel of two dimensional material and a conductive interconnection (9A-C) between the first area and the second area wherein the first area is larger than the second area and wherein the at least one floating electrode is arranged to control the level of doping within the channel of two dimensional material.

A method for fabricating a transistor is provided. The method includes providing a semiconductor substrate; and forming at least a nanowire suspending in the semiconductor substrate. The method also includes forming a channel layer surrounding the nanowire; and forming a contact layer surrounding the channel layer. Further, the method includes forming a trench exposing the channel layer and surrounding the channel layer in the contact layer; and forming a potential barrier layer on the bottom of the trench and surrounding the channel layer. Further, the method also includes forming a gate structure surrounding the potential barrier layer and covering portions of the contact layer; and forming a source and a drain region on the contact layer at two sides of the gate structure, respectively.