A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.

There is provided a semiconductor device (101), including: a first semiconductor layer (25) having a main surface that is a growth surface in a lamination direction and a first side surface (251) disposed at a first angle; and a second semiconductor layer (24) adjacent the first semiconductor layer (25) having a second side surface (241) extending from the first side surface (251) of the first semiconductor layer (25) at a second angle different from the first angle.

An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The p-type contact layer and electron blocking layer can be doped with a p-type dopant. The dopant concentration for the electron blocking layer can be at most ten percent the dopant concentration of the p-type contact layer. A method of designing such a heterostructure is also described.

Disclosed is an ultraviolet light-emitting device. The light-emitting device includes: an n-type contact layer including a GaN layer; a p-type contact layer including an AlGaN or AlInGaN layer; and an active region of multiple quantum well structure positioned between the n-type contact layer and the p-type contact layer. In addition, the active region of multiple quantum well structure includes a GaN or InGaN layer with a thickness less than 2 nm, radiating an ultraviolet ray with a peak wavelength of 340 nm to 360 nm.

Disclosed is a semiconductor light emitting device including: multiple semiconductor layers including a first semiconductor layer, a second semiconductor layer, and an active layer; an electrode electrically connected with the multiple semiconductor layers; a light absorption barrier disposed about at least the electrode; and a non-conductive reflective film adapted to cover the multiple semiconductor layers, the light absorption barrier and the electrode and to reflect light from the active layer, wherein the non-conductive reflective film has an abnormal region of a lower reflectivity around the electrode due to a height difference between the light absorption barrier and the electrode, wherein a portion of the non-conductive reflective film exposed from the electrode is made longer than the abnormal region as seen in a cross-sectional view of the electrode.

A nitride-semiconductor light-emitting element includes an n-type nitride-semiconductor layer, a p-type nitride-semiconductor layer, and a light-emitting layer between the n-type nitride-semiconductor layer and the p-type nitride-semiconductor layer. The light-emitting layer has one or more quantum well layers and two or more barrier layers between which the quantum well layer(s) lie. A first barrier layer, which is the closest of the two or more barrier layers to the p-type nitride-semiconductor layer, has a thickness equal to or smaller than that of the barrier layer(s) different from the first. There is an undoped layer, a layer of a nitride semiconductor represented by a general formula Al.sub.sGa.sub.tIn.sub.uN (0<s<1, 0<t<1, 0u<1, and s+t+u=1), between the first barrier layer and the p-type nitride-semiconductor layer.

A light emitting diode includes a transparent substrate and a GaN buffer layer on the transparent substrate. An n-GaN layer is formed on the buffer layer. An active layer is formed on the n-GaN layer. A p-GaN layer is formed on the active layer. A p-electrode is formed on the p-GaN layer and an n-electrode is formed on the n-GaN layer. A reflective layer is formed on a second side of the transparent substrate. Also, a cladding layer of AlGaN is between the p-GaN layer and the active layer.

A nitride light-emitting diode includes a substrate, an n-type nitride layer, a light-emitting layer, a p-type nitride layer, a p+ layer, an AlInN layer, an n+ layer, and an ITO transparent electrode. A tunneling structure with an AlInN intermediate layer is adopted as the contact layer, which generates polarization charges at the tunneling junction interface and maintains effective width of the depletion region, thereby increasing tunneling probability of holes and reducing contact resistances.

A semiconducting structure configured to emit electromagnetic radiation. The structure includes a first zone and a second zone with first and second types of conductivities respectively opposite to each other, the first and second zones being connected to each other to form a semiconducting junction. The first zone includes at least a first and a second part, the first and the second parts being separated from each other by an intermediate layer, as a spreading layer, extending approximately parallel to a junction plane along a major part of the junction. The spreading layer can cause spreading of carriers in the plane of the spreading layer.

A nitride semiconductor structure and a semiconductor light emitting device including the same are revealed. The nitride semiconductor structure includes a multiple quantum well structure formed by a plurality of well layers and barrier layers stacked alternately. One well layer is disposed between every two barrier layers. The barrier layer is made of Al.sub.xIn.sub.yGa.sub.1-x-yN (0<x<1, 0<y<1, 0<x+y<1) while the well layer is made of In.sub.zGa.sub.1-zN (0<z<1). Thereby quaternary composition is adjusted for lattice match between the barrier layers and the well layers. Thus crystal defect caused by lattice mismatch is improved.