The disclosure relates to a technical field of a semiconductor optoelectronic device, and more particularly, to a light emitting diode and a light emitting device. To solve an issue that a metal layer of the existing light emitting diode has insufficient adhesion on an insulation layer, the light emitting diode includes a semiconductor epitaxial stack layer including a first conductive semiconductor layer, a light emitting layer, and a second conductive semiconductor layer sequentially stacked and disposed; an interface transition layer located above the semiconductor epitaxial stack layer; the interface transition layer including an insulation metal oxide or a stack layer of the insulation metal oxides; a first insulation layer disposed between the interface transition layer and the semiconductor epitaxial stack layer; the metal layer covering a portion of a surface of the interface transition layer and electrically connected to the semiconductor epitaxial stack layer.

Provided are optical transformer devices having a high power efficiency. The device architecture provides uniform current spreading to minimize efficiency droop. The quantum well designs are optimized for both light-emitting diode (LED) and photo diode (PD) operation. A low-loss optical cavity allows efficient transfer of light from the LED junction to the PD junction. The architecture provides a low-loss voltage up- and down-conversion and provides compatibility with production-grade epitaxial growth and wafer fabrication processes.

In an embodiment an optoelectronic component with an epitaxial layer sequence comprises a functional inner region having a first electrical contact and a second electrical contact opposite the first electrical contact, as well as semiconductor layers arranged between the first electrical contact and the second electrical contact configured to generate light. The semiconductor layers comprise a base area that increases towards the second electrical contact. A dielectric passivation layer is arranged on the side walls of the semiconductor layers. A mirror layer surrounds the passivation layer at a distance thereby forming a gap. The second electrical contact and a plane of the gap surrounding the second electrical contact form a common light-emitting surface.

The invention disclosed a preparation method for a high-voltage LED device integrated with a pattern array, comprising the following process steps: providing a substrate, and forming a N-type GaN limiting layer, an epitaxial light-emitting layer and a P-type GaN limiting layer on the substrate in sequence; isolating the N-GaN limiting layer, the epitaxial light-emitting layer and the P-GaN limiting layer on the substrate into at least two or more independent pattern units by means of photo lithography and etching process, wherein each of the pattern unit is in a triangular shape, and very two adjacent pattern units are arranged in an opposing and crossed manner to form a quadrangle, and the quadrangles formed by a plurality of adjacent pattern units are distributed in array; and connecting each pattern unit with metal wires to form a series connection and/or a parallel connection, thereby forming a plurality of interconnected LED chips. For the purpose of improving the current distribution so as to increase the luminescent efficiency of the device, a current blocking layer is also arranged beneath the P-type metal contact of each unit; in addition, an insulation material is also arranged to cover the surface of the chip so as to achieve the purposes of protecting the chip and increasing the light extraction efficiency of the chip.

A light emitting diode (LED) includes a substrate, a first semiconductor layer disposed on the substrate, an active layer disposed on a portion of the first semiconductor layer, a second semiconductor layer disposed on the active layer, a first conductive layer disposed on a portion of the first semiconductor layer, a second conductive layer disposed on the second semiconductor layer, and an insulating layer overlapping the first semiconductor layer, the second semiconductor layer, and the reflection pattern, in which the insulating layer has a first region having different thicknesses and a second region having a substantially constant thickness.

Diode includes first metal layer, coupled to p-type III-N layer and to first terminal, has a substantially equal lateral size to the p-type III-N layer. Central portion of light emitting region on first side and first metal layer includes first via that is etched through p-type portion, light emitting region and first part of n-type III-N portion. Second side of central portion of light emitting region that is opposite to first side includes second via connected to first via. Second via is etched through second part of n-type portion. First via includes second metal layer coupled to intersection between first and second vias. Electrically-insulating layer is coupled to first metal layer, first via, and second metal layer. First terminals are exposed from electrically-insulating layer. Third metal layer including second terminal is coupled to n-type portion on second side of light emitting region and to second metal layer through second via.

A contact to a semiconductor heterostructure is described. In one embodiment, there is an n-type semiconductor contact layer. A light generating structure formed over the n-type semiconductor contact layer has a set of quantum wells and barriers configured to emit or absorb target radiation. An ultraviolet transparent semiconductor layer having a non-uniform thickness is formed over the light generating structure. A p-type contact semiconductor layer having a non-uniform thickness is formed over the ultraviolet transparent semiconductor layer.

The invention relates in particular to a method for producing subsequent patterns in an underlying layer (120), the method comprising at least one step of producing prior patterns in a carbon imprintable layer (110) on top of the underlying layer (120), the production of the prior patterns involving nanoimprinting of the imprintable layer (110) and leave in place a continuous layer formed by the imprintable layer (110) and covering the underlying layer (120), characterized in that it comprises the following step: at least one step of modifying the underlying layer (120) via ion implantation (421) in the underlying layer (120), the implantation (421) being carried out through the imprintable layer (110) comprising the subsequent patterns, the parameters of the implantation (421) being chosen in such a way as to form, in the underlying layer (120), implanted zones (122) and non-implanted zones, the non-Implanted zones defining the subsequent patterns and having a geometry that is dependent on the prior patterns.

A light emitting device includes a base member; a light emitting element mounted on the base member; a light-transmissive member that covers an upper surface of the light emitting element, and is substantially rectangular in a plan view; and a light reflecting member that covers a lateral surface of the light-transmissive member, the light reflecting member having a substantially rectangular frame shape in a plan view. A width of the light reflecting member is smaller along a short side of the light-transmissive member than along a long side of the light-transmissive member. A height of the light reflecting member is smaller along the short side of the light-transmissive member than along the long side of the light-transmissive member at a position separated from an outer edge of the light reflecting member by a predetermined distance.

A light-emitting device includes a first semiconductor layer; a first, a second and a third light-emitting structures formed on the same first semiconductor layer; a first trench between the first and the second light-emitting structures; a second trench between the second and the third light-emitting structures, wherein the first and the second trenches include bottom portions exposing a surface of the first semiconductor layer; a third trench in one of the light-emitting structures, exposing the first semiconductor layer and extending along a direction parallel with the first semiconductor layer; an insulating bridge part in the first and the second trenches, connecting the light-emitting structures; a first electrode in the third trench, electrically connecting to the first semiconductor layer; and a second electrode, including a pad on one of the light-emitting structures and an extending part; wherein the extending part is formed on the insulating bridge part and extends to the light-emitting structures.