Solid state transducer devices having integrated electrostatic discharge protection and associated systems and methods are disclosed herein. In one embodiment, a solid state transducer device includes a solid state emitter, and an electrostatic discharge device carried by the solid state emitter. In some embodiments, the electrostatic discharge device and the solid state emitter share a common first contact and a common second contact. In further embodiments, the solid state lighting device and the electrostatic discharge device share a common epitaxial substrate. In still further embodiments, the electrostatic discharge device is positioned between the solid state lighting device and a support substrate.

A substrate comprising a III-N base layer comprising a first portion and a second portion, the first portion of the III-N base layer having a first natural lattice constant and a first dislocation density; and a first III-N layer having a second natural lattice constant and a second dislocation density on the III-N base layer, the first III-N layer having a thickness greater than 10 nm. An indium fractional composition of the first III-N layer is greater than 0.1; the second natural lattice constant is at least 1% greater than the first natural lattice constant; a strain-induced lattice constant of the first III-N layer is greater than 1.0055 times the first natural lattice constant; and the second dislocation density is less than 1.5 times the first dislocation density.

A light emitting element includes a semiconductor core having at least a partial region extending in a direction and including a first end, a second end, and a main body part between the first end and the second end; a first electrode layer surrounding the second end of the semiconductor core; a second electrode layer surrounding at least the first end of the semiconductor core and spaced apart from the first electrode layer; and an insulating layer surrounding the semiconductor core, the first electrode layer and the second electrode layer. The second end of the semiconductor core has a diameter smaller than a diameter of the main body part.

This invention is related to LED Light Extraction for optoelectronic applications. More particularly the invention relates to (Al, Ga, In)N combined with optimized optics and phosphor layer for highly efficient (Al, Ga, In)N based light emitting diodes applications, and its fabrication method. A further extension is the general combination of a shaped high refractive index light extraction material combined with a shaped optical element.

The invention disclosed a preparation method for a high-voltage LED device integrated with a pattern array, comprising the following process steps: providing a substrate, and forming a N-type GaN limiting layer, an epitaxial light-emitting layer and a P-type GaN limiting layer on the substrate in sequence; isolating the N-GaN limiting layer, the epitaxial light-emitting layer and the P-GaN limiting layer on the substrate into at least two or more independent pattern units by means of photo lithography and etching process, wherein each of the pattern unit is in a triangular shape, and very two adjacent pattern units are arranged in an opposing and crossed manner to form a quadrangle, and the quadrangles formed by a plurality of adjacent pattern units are distributed in array; and connecting each pattern unit with metal wires to form a series connection and/or a parallel connection, thereby forming a plurality of interconnected LED chips. For the purpose of improving the current distribution so as to increase the luminescent efficiency of the device, a current blocking layer is also arranged beneath the P-type metal contact of each unit; in addition, an insulation material is also arranged to cover the surface of the chip so as to achieve the purposes of protecting the chip and increasing the light extraction efficiency of the chip.

Disclosed are a substrate regeneration method and a regenerated substrate. The substrate regeneration method comprises preparing a substrate having a surface separated from an epitaxial layer. The separated surface includes a convex portion and a concave portion, and the convex portion is comparatively flatter than the concave portion. A crystalline restoration layer is grown on the separated surface. The crystalline restoration layer is grown on the convex portion. Furthermore, a surface roughness improvement layer is grown on the crystalline restoration layer, thereby providing a continuous surface. Accordingly, it is possible to provide a regenerated substrate, which has a flat surface, without using physical polishing or chemical etching technology.

A template for a semiconductor device is made by providing an AGN substrate, growing a first layer of Group III nitrides on the substrate, depositing a thin metal layer on the first layer, annealing the metal such as gold so that it agglomerates to form a pattern of islands on the first layer; transferring the pattern into the first layer by etching then removing excess metal; and then depositing a second Group III nitride layer on the first layer. The second layer, through lateral overgrowth, coalesces over the gaps in the island pattern leaving a smooth surface with low defect density. A Group III semiconductor device may then be grown on the template, which may then be removed. Chlorine gas may be used for etching the pattern in the first layer and the remaining gold removed with aqua regia.

Disclosed are a light emitting diode and a light emitting diode module. The light emitting diode module includes a printed circuit board and a light emitting diode joined thereto through a solder paste. The light emitting diode includes a first electrode pad electrically connected to a first conductive type semiconductor layer and a second electrode pad connected to a second conductive type semiconductor layer, wherein each of the first electrode pad and the second electrode pad includes at least five pairs of Ti/Ni layers or at least five pairs of Ti/Cr layers and the uppermost layer of Au. Thus a metal element such as Sn in the solder paste is prevented from diffusion so as to provide a reliable light emitting diode module.

A contact to a semiconductor heterostructure is described. In one embodiment, there is an n-type semiconductor contact layer. A light generating structure formed over the n-type semiconductor contact layer has a set of quantum wells and barriers configured to emit or absorb target radiation. An ultraviolet transparent semiconductor layer having a non-uniform thickness is formed over the light generating structure. A p-type contact semiconductor layer having a non-uniform thickness is formed over the ultraviolet transparent semiconductor layer.

There is provided a method for manufacturing a nanostructure semiconductor light emitting device, including: forming a mask having a plurality of openings on a base layer; growing a first conductivity-type semiconductor layer on exposed regions of the base layer such that the plurality of openings are filled, to form a plurality of nanocores; partially removing the mask such that side surfaces of the plurality of nanocores are exposed; heat-treating the plurality of nanocores after partially removing the mask; sequentially growing an active layer and a second conductivity-type semiconductor layer on surfaces of the plurality of nanocores to form a plurality of light emitting nanostructures, after the heat treatment; and planarizing upper parts of the plurality of light emitting nanostructures such that upper surfaces of the nanocores are exposed.