According to one embodiment, a semiconductor device includes a substrate and a gate electrode. The gate electrode includes a first electrode formed on the substrate, the first electrode having a first conductive property, with a first insulating film between the first electrode and the substrate, and a second electrode formed on the substrate, the second electrode having a second conductive property different from the first conductive property, with a second insulating film between the second electrode and the substrate. The first electrode is formed in a rectangular shape having a hollow portion. A slit is formed in a side surface of the first electrode extending in a width direction of the gate electrode. The second electrode is formed in the slit and along the side surface of the first electrode that has the slit.

Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.

A method of forming a SiOCN material layer, a material layer stack, a semiconductor device, a method of fabricating a semiconductor device, and a deposition apparatus, the method of forming a SiOCN material layer including providing a substrate; providing a silicon precursor onto the substrate; providing an oxygen reactant onto the substrate; providing a first carbon precursor onto the substrate; providing a second carbon precursor onto the substrate; and providing a nitrogen reactant onto the substrate, wherein the first carbon precursor and the second carbon precursor are different materials.

Semiconductor devices and methods for forming semiconductor devices are provided. A vertical channel structure extends from a substrate and is formed as a channel between a source region and a drain region. A first metal gate surrounds a portion of the vertical channel structure and has a gate length. The first metal gate has a first gate section with a first workfunction and a first thickness. The first metal gate also has a second gate section with a second workfunction and a second thickness. The first thickness is different from the second thickness, and the sum of the first thickness and the second thickness is equal to the gate length. A ratio of the first thickness to the second thickness is chosen to achieve a desired threshold voltage level for the semiconductor device.

A method of filling trenches between gates includes forming a first and a second dummy gate over a substrate, the first and second dummy gates including a sacrificial gate material and a hard mask layer; forming a first gate spacer along a sidewall of the first dummy gate and a second gate spacer along a sidewall of the second dummy gate; performing an epitaxial growth process to form a source/drain on the substrate between the first and second dummy gates; disposing a conformal liner over the first and second dummy gates and the source/drain; disposing an oxide on the conformal liner between the first and second dummy gates; recessing the oxide to a level below the hard mask layers of the first and second dummy gates to form a recessed oxide; and depositing a spacer material over the recessed oxide between the first dummy gate and the second dummy gate.

A semiconductor structure includes a trench isolation structure, a trench capping layer, a gate structure and a sidewall spacer. The trench isolation structure includes a first electrically insulating material. The trench capping layer is provided over the trench isolation structure. The trench capping layer includes a second electrically insulating material that is different from the first electrically insulating material. The gate structure includes a gate insulation layer including a high-k material and a gate electrode over the gate insulation layer. The gate structure has a first portion over the trench capping layer. The sidewall spacer is provided adjacent the gate structure. A portion of the sidewall spacer is provided on the trench capping layer and contacts the trench capping layer laterally of the gate insulation layer.

A metal-oxide-semiconductor transistor includes a substrate, a gate insulating layer disposed on the surface of the substrate layer, a metal gate disposed on the gate insulating layer and having at least one plug hole, at least one dielectric plug disposed in the plug hole, and two diffusion regions disposed at two sides of the metal gate in the substrate. The metal gate is configured to operate under an operation voltage greater than 5 v.

A semiconductor integrated circuit device may include a semiconductor substrate, a source pattern, a drain pattern, a nano wire pattern and a gate. The source pattern may be formed on an upper surface of the semiconductor substrate. The drain pattern may be formed on the upper surface of the semiconductor substrate. The drain pattern may be spaced apart from the source pattern. The nano wire pattern may be arranged between the source pattern and the drain pattern. The gate may be configured to surround the nano wire pattern. The nano wire pattern may include an inner wire and an outer wire. The inner wire may include a first semiconductor material. The outer wire may include a second semiconductor material having a band gap greater than a band gap of the first semiconductor material. The outer inner may be formed on an outer surface of the inner wire.

A semiconductor device with multi-level work function and multi-valued channel doping is provided. The semiconductor device comprises a nanowire structure and a gate region. The nanowire structure is formed as a channel between a source region and a drain region. The nanowire structure has a first doped channel section joined with a second doped channel section. The first doped channel section is coupled to the source region and has a doping concentration greater than the doping concentration of the second doped channel section. The second doped channel section is coupled to the drain region. The gate region is formed around the junction at which the first doped section and the second doped section are joined. The gate region has a first work function gate section joined with a second work function gate section. The first work function gate section is located adjacent to the source region and has a work function greater than the work function of the second work function gate section. The second work function gate section located adjacent to the drain region.

Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.